Capacitive digital-to-analog converters (DACs) with shaped output current are disclosed. In certain embodiments, a capacitive DAC converter cell for a capacitive DAC includes a capacitor connected between an output terminal and an internal node, a first current source, a first switch connected in series with the first current source between the internal node and a first voltage, a second current source, a second switch connected in series with the second current source between the internal node and a second voltage, a third switch connected between the internal node and the first voltage, and a fourth switch connected between the internal node and the second voltage.

A current mirror circuit includes a first MOS-type transistor and a second MOS-type transistor assembled as a current mirror, wherein the first transistor has a first gate length different from a second gate length of the second transistor.

A current mirror circuit includes a first MOS-type transistor and a second MOS-type transistor assembled as a current mirror, wherein the first transistor has a first gate length different from a second gate length of the second transistor.

A multipath D/A converter is provided and has input terminals for a first and a second digital signal, and a signal combination unit D/A converting the digital signals supplied to the input terminals, and combining the generated analog signals. The signal combination unit includes a clock signal with a period having a first half period and a second half period. The signal combination unit combines the analog first and second signals by aggregating them with respective weighting coefficients. The signal combination unit has an output terminal for issuing an analog signal based on the aggregation. The signal combination unit applies a first set of weighting coefficients during the first half period of each period and a second set of weighting coefficients during said second half period of each period. The first set of weighting coefficients differs from the second set of weighting coefficients in at least one coefficient.

Methods and systems for electro-absorption modulator drivers in CMOS may comprise an electro-absorption modulator optically coupled to a laser source and electrically coupled to a modulator driver circuit that is in a complementary metal oxide semiconductor (CMOS) chip. The electro-absorption modulator includes a summer for receiving a negative bias voltage and a programmable offset voltage, a voltage regulator for receiving the output of the summer and generating a negative DC voltage of lower magnitude than the negative bias voltage, level shifting circuitry for shifting a received data signal to a DC voltage level between the negative DC voltage from the voltage regulator and the negative bias voltage, and an electrical coupling structure for DC-coupling the level shifted data signal to the modulator. The bias voltage may be received from an off-chip low drop out (LDO) voltage regulator. The level shifting circuitry may include cascode CMOS transistors and a current mirror.

Methods and systems for electro-absorption modulator drivers in CMOS may comprise an electro-absorption modulator optically coupled to a laser source and electrically coupled to a modulator driver circuit that is in a complementary metal oxide semiconductor (CMOS) chip. The electro-absorption modulator includes a summer for receiving a negative bias voltage and a programmable offset voltage, a voltage regulator for receiving the output of the summer and generating a negative DC voltage of lower magnitude than the negative bias voltage, level shifting circuitry for shifting a received data signal to a DC voltage level between the negative DC voltage from the voltage regulator and the negative bias voltage, and an electrical coupling structure for DC-coupling the level shifted data signal to the modulator. The bias voltage may be received from an off-chip low drop out (LDO) voltage regulator. The level shifting circuitry may include cascode CMOS transistors and a current mirror.

The disclosure relates to an error-compensated direct digital modulation device, including: a direct digital radio frequency modulator (DDRM), configured to generate a radio frequency (RF) signal based on a modulation of a digital baseband signal; an error estimator configured to determine an error signal resulting from a deviation based on the generated RF signal and a representation of the digital baseband signal; and an error compensator configured to subtract the error signal from the RF signal to provide an error compensated RF signal.

A smart sensor system can include one or more configurable input and output channels, each configurable channel including one or more switches configured to activate the input and/or output and/or to select a type of input and/or output signal, at least one analog-to-digital converter and at least one digital-to-analog converter operatively connected to the one or more switches for the one or more configurable channels, and at least one controller configured to control the configurable channels.

Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.

Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.