The disclosed system and method provide for a CATV power amplifier in which power dissipation may be reduced by dynamically adjusting the amplifier bias such that the bias is high only when high peak output signals need to be produced. By combining a bias control signal and an RF data signal into a single signal produced by a single DA converter, the disclosed examples require fewer DA converters and a need to synchronize DA converters to produce each of the signals individually is eliminated. A low frequency signal may be added to the RF band to find an optimum compromise between positive and negative peak excursions produced by the amplifier such that an overall reduction in bias may be achieved.

The disclosed system and method provide for a CATV power amplifier in which power dissipation may be reduced by dynamically adjusting the amplifier bias such that the bias is high only when high peak output signals need to be produced. By combining a bias control signal and an RF data signal into a single signal produced by a single DA converter, the disclosed examples require fewer DA converters and a need to synchronize DA converters to produce each of the signals individually is eliminated. A low frequency signal may be added to the RF band to find an optimum compromise between positive and negative peak excursions produced by the amplifier such that an overall reduction in bias may be achieved.

The disclosure is directed to an OFDM receiver with a low-resolution ADC and an electronic device thereof. According to one of the exemplary embodiments, the OFDM receiver may include not limited to: an ADC module which receives a transmission signal of a channel in an analog format and digitizes the transmission signal into a digital format to generate a quantized transmission signal; an error compensating and estimating module which is coupled to the ADC module, receives the quantized transmission signal and a feedback signal which is a first estimated time-domain transmission signal to generate an estimated error signal according to a turbo iterative updating technique; and a signal estimating module which is coupled to the error compensating and estimating module, receives the estimated error signal and a channel attenuation coefficient of the channel to generate an estimated transmission signal.

A device has a digital-to-analog converter to convert waveform data into analog waveforms, a waveform memory to store stored waveform data, an external waveform interface to receive real-time waveform data from an external device, a waveform multiplexer connected to the digital-to-analog converter to select between the first memory and the external waveform interface, a sequencer to receive and execute instructions to identify and access waveform data to drive the digital-to-analog converter, a sequencer instruction memory to provide stored instructions to the sequencer, an external instruction interface to receive real-time instructions for the sequencer, and a sequencer multiplexer to select between the sequencer instruction memory and the external instruction interface connected to the sequencer. A method of controlling a waveform generator includes selecting a mode of operation, where the mode of operation is selected from streaming waveform data, real-time waveform memory updates, real-time sequencer instructions, real-time sequencer instruction updates, and real-time sequencer flow control.

A playback path may include an input configured to receive an input signal, an output configured to drive a differential output signal, a differential current-mode digital-to-analog converter configured to convert the input signal into the differential output signal, and a control circuit. The differential current-mode digital-to-analog converter may include a plurality of current-mode digital-to-analog elements configured to be selectively enabled and disabled based on the input signal and at least one reference element in a current mirror relationship with the plurality of current-mode digital-to-analog elements such that each individual current through each current-mode digital-to-analog element is a scaled version of a reference current of the at least one reference element. The control circuit may be configured to scale current mirror ratios between the at least one reference element and the plurality of current-mode digital-to-analog elements based on a characteristic of the input signal.

The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the same number of the inputted digital bits; a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit; a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the gate of the second MOS tube receives a row blank signal; and a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded. Using the above circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost.

The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the same number of the inputted digital bits; a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit; a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the gate of the second MOS tube receives a row blank signal; and a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded. Using the above circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost.

The present disclosure relates to a source drive IC of liquid crystal panels. The source drive IC includes a digital signals module, a Gamma reference voltage module, a comparator, a power voltage module, a selector, a digital-to-analog converter (DAC) and a buffer amplifier. In addition, a driving method of liquid crystal panels may reduce the power consumption of the buffer amplifier to decrease the temperature of the source drive IC so as to enhance the reliability of the liquid crystal panel.

The present disclosure relates to a source drive IC of liquid crystal panels. The source drive IC includes a digital signals module, a Gamma reference voltage module, a comparator, a power voltage module, a selector, a digital-to-analog converter (DAC) and a buffer amplifier. In addition, a driving method of liquid crystal panels may reduce the power consumption of the buffer amplifier to decrease the temperature of the source drive IC so as to enhance the reliability of the liquid crystal panel.

Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.