Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

Devices and methods for digital to analogue conversion (DAC) are provided, in which the analogue outputs of an even number of digital to analogue converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analogue outputs are subtracted. Dither and filtering techniques may also be employed.

A digital to analog converter includes N lines of transistors. A number of each rear line of transistors is equal to a half of a number of each adjacent front line of transistors. Each transistor includes a conducting terminal, an input terminal, and an output terminal. In any two adjacent lines of transistors, input terminals of the first transistors and input terminals of the second transistors of the rear line are connected to output terminals of the first transistors of a front line respectively. Output terminals of the second transistors of the front line are connected to output terminals of the first transistors of the front line. Output terminals of the second transistors of the rear line of transistors are connected to output terminals of the first transistor of the rear line of transistors. Conducting terminals of each line of transistors are connected to each other.

A digital to analog converter includes N lines of transistors. A number of each rear line of transistors is equal to a half of a number of each adjacent front line of transistors. Each transistor includes a conducting terminal, an input terminal, and an output terminal. In any two adjacent lines of transistors, input terminals of the first transistors and input terminals of the second transistors of the rear line are connected to output terminals of the first transistors of a front line respectively. Output terminals of the second transistors of the front line are connected to output terminals of the first transistors of the front line. Output terminals of the second transistors of the rear line of transistors are connected to output terminals of the first transistor of the rear line of transistors. Conducting terminals of each line of transistors are connected to each other.

An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

A method to perform convolutions between arbitrary vectors includes estimating a first degree of match for a difference between a first vector having a plurality of first elements and a second vector having a plurality of second elements using a first cluster of coupled oscillators, estimating a second degree of match for the first vector using a second cluster of coupled oscillators, estimating a third degree of match for the second vector using a third cluster of coupled oscillators, deriving a first squared L.sup.2 norm from the first degree of match, deriving a second squared L.sup.2 norm from the second degree of match, deriving a third squared L.sup.2 norm from the third degree of match, adding the second squared L.sup.2 norm and the third squared L.sup.2 norm, and subtracting the first squared L.sup.2 norm to form a sum, and dividing the sum by two.

A method to perform convolutions between arbitrary vectors includes estimating a first degree of match for a difference between a first vector having a plurality of first elements and a second vector having a plurality of second elements using a first cluster of coupled oscillators, estimating a second degree of match for the first vector using a second cluster of coupled oscillators, estimating a third degree of match for the second vector using a third cluster of coupled oscillators, deriving a first squared L.sup.2 norm from the first degree of match, deriving a second squared L.sup.2 norm from the second degree of match, deriving a third squared L.sup.2 norm from the third degree of match, adding the second squared L.sup.2 norm and the third squared L.sup.2 norm, and subtracting the first squared L.sup.2 norm to form a sum, and dividing the sum by two.

A method in a transmitter circuit (200) of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first CP of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating (100) the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting (110) a sampling phase during CPs.

Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.