A switched current source circuit, comprising first and second voltage source nodes; a load; a current source; and capacitor switching circuitry comprising a load node, a capacitor and a plurality of switches configured, based on a control signal, to adopt a biasing configuration followed by an active configuration, wherein in the biasing configuration, the load node is conductively connected to the second voltage source node to bias a voltage level at the load node, and the capacitor is connected so that it at least partly charges; and in the active configuration, the load node is conductively connected via the load to the first voltage source node, and via the capacitor to the current source to increase a potential difference between the first voltage source node and the load node.

The present disclosure provides a control system comprising at least one measurement signal path configured to measure a state of at least one respective qubit, a digital signal generation signal path for each qubit, wherein the signal generation signal path is configured to generate at least one digital control signal for the respective qubit, in each digital signal generation signal path, a digital switch for each digital control signal, wherein the digital switch is configured to controllably pass through the respective digital control signal to an output of the digital signal generation signal path or to block the respective digital control signal based on the measured state of the respective qubit, and an analog signal path for each digital signal generation signal path, wherein the analog signal path is coupled to the output of the respective digital signal generation signal path and configured to generate an analog control pulse waveform for the respective qubit based on the at least one digital control signal. The present disclosure further provides a control method, and a quantum computer system.

The present disclosure provides a control system comprising at least one measurement signal path configured to measure a state of at least one respective qubit, a digital signal generation signal path for each qubit, wherein the signal generation signal path is configured to generate at least one digital control signal for the respective qubit, in each digital signal generation signal path, a digital switch for each digital control signal, wherein the digital switch is configured to controllably pass through the respective digital control signal to an output of the digital signal generation signal path or to block the respective digital control signal based on the measured state of the respective qubit, and an analog signal path for each digital signal generation signal path, wherein the analog signal path is coupled to the output of the respective digital signal generation signal path and configured to generate an analog control pulse waveform for the respective qubit based on the at least one digital control signal. The present disclosure further provides a control method, and a quantum computer system.

Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.

Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.

A combined radio frequency (RF) digital-to-analog converter (DAC) may include an in-phase and quadrature-(IQ-) based DAC to generate a phase component of an output RF signal and a polar-based DAC to generate an amplitude component of the RF signal. Additionally, modulation circuitry may combine the amplitude component and the phase component to generate the output RF signal.

A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.

Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partiallye.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

A model identification system includes an analog to digital converter (ADC). The ADC includes a conversion circuit configured to receive a first analog signal and generate a first digital signal including samples having a first rate by sampling the first analog signal at the first rate. The ADC further includes a first digital signal processing (DSP) circuit configured to generate a second digital signal including samples having a second rate less than the first rate based on the second digital signal and a first sampling matrix. The first sampling matrix is a block diagonal matrix including a plurality of diagonal blocks, each diagonal block is a row vector including a plurality of elements.