H03M1/66

METHOD FOR CONTROLLING DIGITAL-TO-ANALOGUE CONVERTERS AND RF TRANSMIT CIRCUIT ARRANGEMENT
20180091203 · 2018-03-29 ·

The invention relates to a method for controlling digital-to-analogue converters (DAC), the method comprising: providing a plurality of digital-to-analogue converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analogue RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analogue RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.

METHOD FOR CONTROLLING DIGITAL-TO-ANALOGUE CONVERTERS AND RF TRANSMIT CIRCUIT ARRANGEMENT
20180091203 · 2018-03-29 ·

The invention relates to a method for controlling digital-to-analogue converters (DAC), the method comprising: providing a plurality of digital-to-analogue converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analogue RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analogue RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.

LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS)
20180091164 · 2018-03-29 ·

Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC.

LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS)
20180091164 · 2018-03-29 ·

Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC.

Therapeutic Tooth Bud Ablation
20180091169 · 2018-03-29 · ·

Ablation probe tips (108, 148, 320, 360) and physical and virtual stents (110) for use in tooth bud ablation procedures that result in tooth agenesis as well as tooth bud ablation methods are described herein.

Therapeutic Tooth Bud Ablation
20180091169 · 2018-03-29 · ·

Ablation probe tips (108, 148, 320, 360) and physical and virtual stents (110) for use in tooth bud ablation procedures that result in tooth agenesis as well as tooth bud ablation methods are described herein.

DIGITAL-TO-ANALOG CONVERTER AND SOURCE DRIVER USING THE SAME
20180091168 · 2018-03-29 · ·

A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

DIGITAL-TO-ANALOG CONVERTER AND SOURCE DRIVER USING THE SAME
20180091168 · 2018-03-29 · ·

A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

PARAMETER CORRECTION FOR CASCADED SIGNAL COMPONENTS
20180090222 · 2018-03-29 ·

Various examples are directed to crosspoint switches and methods of use thereof. An example cross point switch comprises a first row buffer, a second row buffer, a first column buffer, and a second column buffer. The crosspoint switch may also comprise a first switch that, when closed, electrically couples the second row buffer to the first column buffer, and a correction controller. The correction controller may be configured to send a first correction signal to the first row buffer, send a second correction signal to the second row buffer; receive an indication that the first switch is closed, send a third correction signal to the first column buffer; and send a fourth correction signal to the second column buffer.

PARAMETER CORRECTION FOR CASCADED SIGNAL COMPONENTS
20180090222 · 2018-03-29 ·

Various examples are directed to crosspoint switches and methods of use thereof. An example cross point switch comprises a first row buffer, a second row buffer, a first column buffer, and a second column buffer. The crosspoint switch may also comprise a first switch that, when closed, electrically couples the second row buffer to the first column buffer, and a correction controller. The correction controller may be configured to send a first correction signal to the first row buffer, send a second correction signal to the second row buffer; receive an indication that the first switch is closed, send a third correction signal to the first column buffer; and send a fourth correction signal to the second column buffer.