The present disclosure relates to a solid state image sensor and an electronic apparatus capable of performing a gain transition at high speed. A ramp generation circuit includes sample hold circuits and ramp generation DACs, the number of which depends on kinds of required gains (for example, two kinds, i.e. a low gain and a high gain). Then, the two sample hold circuits can individually hold gain DAC output voltages at the different gains. This enables a switch to the ramp generation DAC holding the required gain voltage by means of a ramp selection signal. The present disclosure can be applied, for example, to a CMOS solid state image sensor that is used for an imaging device.

The present disclosure relates to a solid state image sensor and an electronic apparatus capable of performing a gain transition at high speed. A ramp generation circuit includes sample hold circuits and ramp generation DACs, the number of which depends on kinds of required gains (for example, two kinds, i.e. a low gain and a high gain). Then, the two sample hold circuits can individually hold gain DAC output voltages at the different gains. This enables a switch to the ramp generation DAC holding the required gain voltage by means of a ramp selection signal. The present disclosure can be applied, for example, to a CMOS solid state image sensor that is used for an imaging device.

Systems and methods for providing an output signal based at least in part upon an input signal and a clock signal in a manner in which jitter is avoided or diminished, including for example a digital-to-analog converter (DAC), are disclosed herein. In one example embodiment, such a system includes an output signal generating component, a first component having a first switch and a variable characteristic, and a plurality of second components each having a respective additional switch and a respective fixed characteristic. A value of the variable characteristic is set at least in part based upon input and clock signals so that, when the variable characteristic influences at least indirectly the generating of the output signal by the output signal generating component, the output signal attains a first level that at least indirectly depends upon a phase of the clock signal relative to the input signal.

A control circuit for a current switch of a current digital to analog converter (DAC) includes a first inverter, a second inverter, a first pull-low switch, a second pull-low switch and a timing synchronization circuit. The first inverter includes an input terminal and an output terminal. The second inverter includes an input terminal and an output terminal, wherein the input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal of the second inverter is coupled to the input terminal of the first inverter. The first pull-low switch is coupled to the input terminal of the first inverter. The second pull-low switch is coupled to the input terminal of the second inverter. The timing synchronization circuit is coupled to the first pull-low switch and the second pull-low switch.

This disclosure describes a precise, fast, and relatively low power current-source for use in various applications, which may include driving power semiconductors such power MOSFETs and IGBTs. The current-source may provide both a constant current and a current profile over time which may charge and discharge the steering terminal (e.g. the gate) of a power semiconductor for precise control of switch timing. The current-source uses current steering digital-to-analog converter (DAC) technology and current mirrors to generate a high output current that is significantly immune to power supply and ground variability.

Digital-to-analog converter (DAC) circuitry for providing currents at electrodes of an Implantable Pulse Generator (IPG) is disclosed. The DAC circuitry includes at least one PDAC for sourcing current to the electrodes, and at least one NDAC for sinking current from the electrodes. The PDACs are powered with power supplies VH (the compliance voltage) and Vssh in a high power domain, and the NDACs are powered with power supplies Vcc and ground in a low power domain. VH may change during IPG operation, and Vssh preferably also changes with a fixed difference with respect to VH. Digital control signals to the PDACs are formed (and possibly converted into) the high power domain, and transistors used to build the PDACs are biased in the high power domain, and thus may also change with VH. This permits transistors in the PDACs and NDACs to be made from normal low-voltage logic transistors.

Improved circuitry for measuring analog values in an implantable pulse generator is disclosed. The measurement circuitry executes instructions that define the timing and parameters of measurements to be taken. The instructions include instructions that are responsive to different types of triggers issued by different pulse definition circuits, which pulse definition circuits generate different stimulation waveforms at different groups of electrodes. The measurement circuitry is configurable to update the groups of electrodes used to deliver stimulation.

Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.

Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.

Methods of generating a gradient waveform, gradient waveform generators and magnetic resonance imaging systems are provided. In one aspect, a first digital value is obtained by quantizing and coding spatial position information of a voxel of a subject according to the number of preset quantization bits, wherein the number of the quantization bits are more than the number of allowed input bits for a DAC; a second digital value is determined to be inputted into the DAC according to the first digital value and the number of the allowed input bits for the DAC; a quantization error is determined according to the first digital value and the second digital value; an error accumulating value is updated by accumulating the quantization error to the error accumulation value; the second digital value corrected according to the error accumulation value; and the corrected second digital value is inputted into the DAC.