Methods of generating a gradient waveform, gradient waveform generators and magnetic resonance imaging systems are provided. In one aspect, a first digital value is obtained by quantizing and coding spatial position information of a voxel of a subject according to the number of preset quantization bits, wherein the number of the quantization bits are more than the number of allowed input bits for a DAC; a second digital value is determined to be inputted into the DAC according to the first digital value and the number of the allowed input bits for the DAC; a quantization error is determined according to the first digital value and the second digital value; an error accumulating value is updated by accumulating the quantization error to the error accumulation value; the second digital value corrected according to the error accumulation value; and the corrected second digital value is inputted into the DAC.

Methods of generating a gradient waveform, gradient waveform generators and magnetic resonance imaging systems are provided. In one aspect, a first digital value is obtained by quantizing and coding spatial position information of a voxel of a subject according to the number of preset quantization bits, wherein the number of the quantization bits are more than the number of allowed input bits for a DAC; a second digital value is determined to be inputted into the DAC according to the first digital value and the number of the allowed input bits for the DAC; a quantization error is determined according to the first digital value and the second digital value; an error accumulating value is updated by accumulating the quantization error to the error accumulation value; the second digital value corrected according to the error accumulation value; and the corrected second digital value is inputted into the DAC.

Methods of generating a gradient waveform, gradient waveform generators and magnetic resonance imaging systems are provided. In one aspect, a first digital value is obtained by quantizing and coding spatial position information of a voxel of a subject according to the number of preset quantization bits, wherein the number of the quantization bits are more than the number of allowed input bits for a DAC; a second digital value is determined to be inputted into the DAC according to the first digital value and the number of the allowed input bits for the DAC; a quantization error is determined according to the first digital value and the second digital value; an error accumulating value is updated by accumulating the quantization error to the error accumulation value; the second digital value corrected according to the error accumulation value; and the corrected second digital value is inputted into the DAC.

Methods of generating a gradient waveform, gradient waveform generators and magnetic resonance imaging systems are provided. In one aspect, a first digital value is obtained by quantizing and coding spatial position information of a voxel of a subject according to the number of preset quantization bits, wherein the number of the quantization bits are more than the number of allowed input bits for a DAC; a second digital value is determined to be inputted into the DAC according to the first digital value and the number of the allowed input bits for the DAC; a quantization error is determined according to the first digital value and the second digital value; an error accumulating value is updated by accumulating the quantization error to the error accumulation value; the second digital value corrected according to the error accumulation value; and the corrected second digital value is inputted into the DAC.

Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Systems and methods are provided for adaptive configuration and control of digital-to-analog converters (DACs). Performance of a plurality of conversion elements in a digital-to-analog converter (DAC) may be assessed based on particular input conditions associated with a digital input to the DAC, and the DAC may be configured based on the assessing of performance. Each conversion element of the plurality of conversion elements handles a particular bit in the digital input. The configuring may comprise selecting a subset of the plurality of conversion elements, and setting only the subset of the plurality of conversion elements to apply a particular type of operations. The particular type of operations pertains to applying digital-to-analog conversions via the DAC, and the particular type of operations relates to or affects performance. The particular input conditions may comprise signal backoff.

To perform processing at a higher speed cycle. A high-speed converter (220) includes any conversion means (241, 251, 261, 271) among a first conversion means (241) for converting an analog signal into a digital value; a second conversion means (251) for converting a digital value into an analog signal; a third conversion means (261) for converting an electrical signal into a digital signal; and a fourth conversion means (271) for converting a digital signal into an electrical signal, and causes the conversion means (241, 251, 261, 271) that is included to operate by a method based on information acquired via a network (400).

The present invention discloses a digital to analog conversion module, a data drive circuit and a liquid crystal display, wherein the digital to analog conversion module can comprise 2N1 sub circuits and 2N11 first divider resistors, and each sub circuit comprises a second divider resistor, a first switch circuit and a second switch circuit, wherein the first switch circuit and the second switch circuit are respectively coupled to two ends of the second divider resistor; the first switch circuit comprises N first switch units coupled in series, and the second switch circuit comprises a second switch unit and at least one first switch unit coupled in series; according to a preset order, a control end of the second switch unit is coupled to a connection node of a N1th and a Nth first switch units; an output end of the second switch unit is coupled to the first switch unit.

The present invention discloses a digital to analog conversion module, a data drive circuit and a liquid crystal display, wherein the digital to analog conversion module can comprise 2N1 sub circuits and 2N11 first divider resistors, and each sub circuit comprises a second divider resistor, a first switch circuit and a second switch circuit, wherein the first switch circuit and the second switch circuit are respectively coupled to two ends of the second divider resistor; the first switch circuit comprises N first switch units coupled in series, and the second switch circuit comprises a second switch unit and at least one first switch unit coupled in series; according to a preset order, a control end of the second switch unit is coupled to a connection node of a N1th and a Nth first switch units; an output end of the second switch unit is coupled to the first switch unit.