The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

An apparatus for compensating for nonlinearities in a DAC caused by variabilities of a power supply. The apparatus may include a power supply, a processing component, and a front-end circuit. The power supply may generate power, where the power includes variabilities in a power. The processing component may generate a digital signal. The front-end circuit may be operatively coupled to the power supply and the processing component. The front-end circuit may receive the power from the power supply, identify the nonlinearities in the power, receive the digital signal from the processing component, and adjust the digital signal for the nonlinearities to obtain an input signal to send to a digital to analog converter (DAC).

An apparatus for compensating for nonlinearities in a DAC caused by variabilities of a power supply. The apparatus may include a power supply, a processing component, and a front-end circuit. The power supply may generate power, where the power includes variabilities in a power. The processing component may generate a digital signal. The front-end circuit may be operatively coupled to the power supply and the processing component. The front-end circuit may receive the power from the power supply, identify the nonlinearities in the power, receive the digital signal from the processing component, and adjust the digital signal for the nonlinearities to obtain an input signal to send to a digital to analog converter (DAC).

An apparatus comprised of a cascaded series of optical modulators addressed by a multi-bit digital word with each optical modulator in the cascaded series being responsive to a single bit in the multi-bit digital word and wherein each of the optical modulators in the cascaded series of optical modulators doubling in effective optical length as a bit index of the bit of the multi-bit digital word to which it is responsive increases by a bit index value equal to one. The apparatus may be used with a prior art analog optical modulator and an associated ADC, having a fixed bit width, to extend the number of bits beyond the fixed bit width that the ADC and analog optical modulator prior art combination can otherwise operate.

An apparatus comprised of a cascaded series of optical modulators addressed by a multi-bit digital word with each optical modulator in the cascaded series being responsive to a single bit in the multi-bit digital word and wherein each of the optical modulators in the cascaded series of optical modulators doubling in effective optical length as a bit index of the bit of the multi-bit digital word to which it is responsive increases by a bit index value equal to one. The apparatus may be used with a prior art analog optical modulator and an associated ADC, having a fixed bit width, to extend the number of bits beyond the fixed bit width that the ADC and analog optical modulator prior art combination can otherwise operate.

A semi-digital finite impulse response, FIR, filter is configured as a sparse FIR filter and as a minimum phase lag FIR filter. The FIR filter has a delay line composed of a number of sets of delay units sequentially coupled to each other, and where some of the sets of delay units have one or more untapped delay units as part of a cascade of two or more single-sample delay units. An analog summing node is coupled to the taps and produces at its output an analog version of a digital input signal that is fed to an input of the delay line. Other embodiments are also described and claimed.

A semi-digital finite impulse response, FIR, filter is configured as a sparse FIR filter and as a minimum phase lag FIR filter. The FIR filter has a delay line composed of a number of sets of delay units sequentially coupled to each other, and where some of the sets of delay units have one or more untapped delay units as part of a cascade of two or more single-sample delay units. An analog summing node is coupled to the taps and produces at its output an analog version of a digital input signal that is fed to an input of the delay line. Other embodiments are also described and claimed.

A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

Provided is an AD converter including a first AD converting unit in which pixel columns of a pixel array are divided into at least two groups, and that compares a first ramp signal and a first pixel signal output from a first group of the pixel columns and performs AD conversion on the first pixel signal; and a second AD converting unit that compares a second ramp signal and a second pixel signal output from a second group of the pixel columns and performs AD conversion on the second pixel signal, in which the first ramp signal is a signal of which a level is decreased with a constant slope over time in a D-phase period for detecting a signal level of a pixel signal, and the second ramp signal is a signal of which a level is increased with a constant slope over time in the D-phase period.