Methods of generating a gradient waveform, gradient waveform generators and magnetic resonance imaging systems are provided. In one aspect, a first digital value is obtained by quantizing and coding spatial position information of a voxel of a subject according to the number of preset quantization bits, wherein the number of the quantization bits are more than the number of allowed input bits for a DAC; a second digital value is determined to be inputted into the DAC according to the first digital value and the number of the allowed input bits for the DAC; a quantization error is determined according to the first digital value and the second digital value; an error accumulating value is updated by accumulating the quantization error to the error accumulation value; the second digital value corrected according to the error accumulation value; and the corrected second digital value is inputted into the DAC.

Methods of generating a gradient waveform, gradient waveform generators and magnetic resonance imaging systems are provided. In one aspect, a first digital value is obtained by quantizing and coding spatial position information of a voxel of a subject according to the number of preset quantization bits, wherein the number of the quantization bits are more than the number of allowed input bits for a DAC; a second digital value is determined to be inputted into the DAC according to the first digital value and the number of the allowed input bits for the DAC; a quantization error is determined according to the first digital value and the second digital value; an error accumulating value is updated by accumulating the quantization error to the error accumulation value; the second digital value corrected according to the error accumulation value; and the corrected second digital value is inputted into the DAC.

Systems and methods are provided for adaptive configuration and control of digital-to-analog converters (DACs). Performance of a plurality of conversion elements in a digital-to-analog converter (DAC) may be assessed based on particular input conditions associated with a digital input to the DAC, and the DAC may be configured based on the assessing of performance. Each conversion element of the plurality of conversion elements handles a particular bit in the digital input. The configuring may comprise selecting a subset of the plurality of conversion elements, and setting only the subset of the plurality of conversion elements to apply a particular type of operations. The particular type of operations pertains to applying digital-to-analog conversions via the DAC, and the particular type of operations relates to or affects performance. The particular input conditions may comprise signal backoff.

The present invention discloses a digital to analog conversion module, a data drive circuit and a liquid crystal display, wherein the digital to analog conversion module can comprise 2N1 sub circuits and 2N11 first divider resistors, and each sub circuit comprises a second divider resistor, a first switch circuit and a second switch circuit, wherein the first switch circuit and the second switch circuit are respectively coupled to two ends of the second divider resistor; the first switch circuit comprises N first switch units coupled in series, and the second switch circuit comprises a second switch unit and at least one first switch unit coupled in series; according to a preset order, a control end of the second switch unit is coupled to a connection node of a N1th and a Nth first switch units; an output end of the second switch unit is coupled to the first switch unit.

The present invention discloses a digital to analog conversion module, a data drive circuit and a liquid crystal display, wherein the digital to analog conversion module can comprise 2N1 sub circuits and 2N11 first divider resistors, and each sub circuit comprises a second divider resistor, a first switch circuit and a second switch circuit, wherein the first switch circuit and the second switch circuit are respectively coupled to two ends of the second divider resistor; the first switch circuit comprises N first switch units coupled in series, and the second switch circuit comprises a second switch unit and at least one first switch unit coupled in series; according to a preset order, a control end of the second switch unit is coupled to a connection node of a N1th and a Nth first switch units; an output end of the second switch unit is coupled to the first switch unit.

A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.

An apparatus comprised of a cascaded series of optical modulators addressed by a multi-bit digital word with each optical modulator in the cascaded series being responsive to a single bit in the multi-bit digital word and wherein each of the optical modulators in the cascaded series of optical modulators doubling in effective optical length as a bit index of the bit of the multi-bit digital word to which it is responsive increases by a bit index value equal to one. The apparatus may be used with a prior art analog optical modulator and an associated ADC, having a fixed bit width, to extend the number of bits beyond the fixed bit width that the ADC and analog optical modulator prior art combination can otherwise operate.