Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.

An apparatus comprised of a cascaded series of optical modulators addressed by a multi-bit digital word with each optical modulator in the cascaded series being responsive to a single bit in the multi-bit digital word and wherein each of the optical modulators in the cascaded series of optical modulators doubling in effective optical length as a bit index of the bit of the multi-bit digital word to which it is responsive increases by a bit index value equal to one. The apparatus may be used with a prior art analog optical modulator and an associated ADC, having a fixed bit width, to extend the number of bits beyond the fixed bit width that the ADC and analog optical modulator prior art combination can otherwise operate.

An apparatus comprised of a cascaded series of optical modulators addressed by a multi-bit digital word with each optical modulator in the cascaded series being responsive to a single bit in the multi-bit digital word and wherein each of the optical modulators in the cascaded series of optical modulators doubling in effective optical length as a bit index of the bit of the multi-bit digital word to which it is responsive increases by a bit index value equal to one. The apparatus may be used with a prior art analog optical modulator and an associated ADC, having a fixed bit width, to extend the number of bits beyond the fixed bit width that the ADC and analog optical modulator prior art combination can otherwise operate.

A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be LC notch filters (with Ln notch inductors), and the peaking filter can be Ls peaking inductors coupled in series to the LC notch filters. The Ln notch inductors, Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ signal paths are implemented with differential DAC designs including passive reconstruction filters.

DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be LC notch filters (with Ln notch inductors), and the peaking filter can be Ls peaking inductors coupled in series to the LC notch filters. The Ln notch inductors, Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ signal paths are implemented with differential DAC designs including passive reconstruction filters.

Embodiments of the present invention disclose a power line communications device, and the power line communications device includes a USB interface, a protocol conversion module, a signal conversion module, a coupler, and a power line interface. A first end of the USB interface is connected to a first end of the protocol conversion module, a second end of the protocol conversion module is connected to a first end of the signal conversion module, a second end of the signal conversion module is connected to a first end of the coupler, and a second end of the coupler is connected to a first end of the power line interface. During implementation of the embodiments of the present invention, the USB interface may be used to provide a network signal for a terminal device.

Embodiments of the present invention disclose a power line communications device, and the power line communications device includes a USB interface, a protocol conversion module, a signal conversion module, a coupler, and a power line interface. A first end of the USB interface is connected to a first end of the protocol conversion module, a second end of the protocol conversion module is connected to a first end of the signal conversion module, a second end of the signal conversion module is connected to a first end of the coupler, and a second end of the coupler is connected to a first end of the power line interface. During implementation of the embodiments of the present invention, the USB interface may be used to provide a network signal for a terminal device.

Provided is an AD converter including a first AD converting unit in which pixel columns of a pixel array are divided into at least two groups, and that compares a first ramp signal and a first pixel signal output from a first group of the pixel columns and performs AD conversion on the first pixel signal; and a second AD converting unit that compares a second ramp signal and a second pixel signal output from a second group of the pixel columns and performs AD conversion on the second pixel signal, in which the first ramp signal is a signal of which a level is decreased with a constant slope over time in a D-phase period for detecting a signal level of a pixel signal, and the second ramp signal is a signal of which a level is increased with a constant slope over time in the D-phase period.