A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

A semi-digital finite impulse response, FIR, filter is configured as a sparse FIR filter and as a minimum phase lag FIR filter. The FIR filter has a delay line composed of a number of sets of delay units sequentially coupled to each other, and where some of the sets of delay units have one or more untapped delay units as part of a cascade of two or more single-sample delay units. An analog summing node is coupled to the taps and produces at its output an analog version of a digital input signal that is fed to an input of the delay line. Other embodiments are also described and claimed.

A semi-digital finite impulse response, FIR, filter is configured as a sparse FIR filter and as a minimum phase lag FIR filter. The FIR filter has a delay line composed of a number of sets of delay units sequentially coupled to each other, and where some of the sets of delay units have one or more untapped delay units as part of a cascade of two or more single-sample delay units. An analog summing node is coupled to the taps and produces at its output an analog version of a digital input signal that is fed to an input of the delay line. Other embodiments are also described and claimed.

A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be LC notch filters (with Ln notch inductors), and the peaking filter can be Ls peaking inductors coupled in series to the LC notch filters. The Ln notch inductors, Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ signal paths are implemented with differential DAC designs including passive reconstruction filters.

DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be LC notch filters (with Ln notch inductors), and the peaking filter can be Ls peaking inductors coupled in series to the LC notch filters. The Ln notch inductors, Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ signal paths are implemented with differential DAC designs including passive reconstruction filters.

Embodiments of the present invention disclose a power line communications device, and the power line communications device includes a USB interface, a protocol conversion module, a signal conversion module, a coupler, and a power line interface. A first end of the USB interface is connected to a first end of the protocol conversion module, a second end of the protocol conversion module is connected to a first end of the signal conversion module, a second end of the signal conversion module is connected to a first end of the coupler, and a second end of the coupler is connected to a first end of the power line interface. During implementation of the embodiments of the present invention, the USB interface may be used to provide a network signal for a terminal device.