A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

Methods and apparatus for controlling a power supply voltage for a switch driver in a digital-to-analog converter (DAC). An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled in series with the current source at a first node, and a switch driver having an output coupled to a control input of the first switch; and calibration circuitry having a first input coupled to a first DAC cell in the plurality of DAC cells and having an output coupled to at least one of the plurality of DAC cells, the calibration circuitry being configured to sense a voltage of the first node in the first DAC cell and to control the power supply voltage for the switch driver in the at least one of the plurality of DAC cells, based on the sensed voltage of the first node.

There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

An analog-to-digital and digital-to-analog conversion system using pulse-density-modulation (PDM) digital signals which minimize noise and optimize dynamic range by dividing a signal into multiple parallel pathways by apportioning a least significant range portion of an incoming signal to a low-path circuit and a most-significant portion of the incoming signal to a high-path circuit. The high-path circuit and low-path circuit can be separately level-modified to optimize dynamic range. Embodiments of the system can include an analog-to-digital conversion, a digital-to-analog conversion, or a complete analog-to-digital and digital-to-analog conversion system.

A method to perform convolutions between arbitrary vectors includes estimating a first degree of match for a difference between a first vector having a plurality of first elements and a second vector having a plurality of second elements using a first cluster of coupled oscillators, estimating a second degree of match for the first vector using a second cluster of coupled oscillators, estimating a third degree of match for the second vector using a third cluster of coupled oscillators, deriving a first squared L.sup.2 norm from the first degree of match, deriving a second squared L.sup.2 norm from the second degree of match, deriving a third squared L.sup.2 norm from the third degree of match, adding the second squared L.sup.2 norm and the third squared L.sup.2 norm, and subtracting the first squared L.sup.2 norm to form a sum, and dividing the sum by two.

Digital to analog converters have first and second to analog arrays. The first digital to analog array has a reference input, a reference output, a first digital input that is connectable to a digital signal, and an analog output. The second digital to analog array includes a reference input, a reference output that is coupled to the reference input of the first digital to analog array, a plurality of switches coupled to the reference input, and a plurality of resistors coupled between the switches and the reference output.

Certain aspects of the present disclosure provide digital-to-analog converters (DACs). One example DAC generally includes a first transistor configured to selectively couple a power source to a load. In a first mode of operation of the DAC, the first transistor is closed and couples the load to the power source. In a second mode of operation of the DAC, the first transistor is open and decouples the load from the power source. The DAC further includes a current limiting circuit selectively coupled between the first transistor and a reference voltage. In the first mode, the current limiting circuit is decoupled from the reference voltage. In the second mode, the current limiting circuit is coupled to the reference voltage.