H03M1/66

Audio processing apparatus and method having echo canceling mechanism
12176911 · 2024-12-24 · ·

An audio processing apparatus having an echo canceling mechanism is provided. An audio transmission circuit receives an input digital audio signal from an external device. A DAC circuit performs conversion according to the input digital audio signal to generate an output analog audio signal to an external display device for power amplification and playback. An ADC circuit performs analog-to-digital conversion on an amplified signal generated by a power amplification circuit and a received audio signal generated by an audio receiving device to generate an amplified digital signal and a received digital audio signal. A processor implements an echo canceling algorithm to perform echo cancellation according to the amplified digital signal and the received digital audio signal to generate an output digital audio signal to be transmitted to the external device through the audio transmission circuit.

Digital-to-analog converter (DAC) with adaptive calibration scheme
12160244 · 2024-12-03 · ·

Methods and apparatus for controlling a power supply voltage for a switch driver in a digital-to-analog converter (DAC). An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled in series with the current source at a first node, and a switch driver having an output coupled to a control input of the first switch; and calibration circuitry having a first input coupled to a first DAC cell in the plurality of DAC cells and having an output coupled to at least one of the plurality of DAC cells, the calibration circuitry being configured to sense a voltage of the first node in the first DAC cell and to control the power supply voltage for the switch driver in the at least one of the plurality of DAC cells, based on the sensed voltage of the first node.

Clock generation circuitry
09887667 · 2018-02-06 · ·

There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

Clock generation circuitry
09887667 · 2018-02-06 · ·

There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

DA converter, AD converter, and semiconductor device

A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

DA converter, AD converter, and semiconductor device

A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

Multi-path analog-to-digital and digital-to-analog conversion of PDM signals
09871530 · 2018-01-16 ·

An analog-to-digital and digital-to-analog conversion system using pulse-density-modulation (PDM) digital signals which minimize noise and optimize dynamic range by dividing a signal into multiple parallel pathways by apportioning a least significant range portion of an incoming signal to a low-path circuit and a most-significant portion of the incoming signal to a high-path circuit. The high-path circuit and low-path circuit can be separately level-modified to optimize dynamic range. Embodiments of the system can include an analog-to-digital conversion, a digital-to-analog conversion, or a complete analog-to-digital and digital-to-analog conversion system.

Digital to analog conversion with correlated electron switch devices

Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.

Digital to analog conversion with correlated electron switch devices

Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.

METHOD TO PERFORM CONVOLUTIONS BETWEEN ARBITRARY VECTORS USING CLUSTERS OF WEAKLY COUPLED OSCILLATORS

A method to perform convolutions between arbitrary vectors includes estimating a first degree of match for a difference between a first vector having a plurality of first elements and a second vector having a plurality of second elements using a first cluster of coupled oscillators, estimating a second degree of match for the first vector using a second cluster of coupled oscillators, estimating a third degree of match for the second vector using a third cluster of coupled oscillators, deriving a first squared L.sup.2 norm from the first degree of match, deriving a second squared L.sup.2 norm from the second degree of match, deriving a third squared L.sup.2 norm from the third degree of match, adding the second squared L.sup.2 norm and the third squared L.sup.2 norm, and subtracting the first squared L.sup.2 norm to form a sum, and dividing the sum by two.