In an example, a circuit for controlling at least two electronic switches in a parallel configuration between a power supply and a load. The circuit includes a control circuit to generate first and second control signals to control first and second electronic switches of the at least two electronic switches, and establish a conduction sequence of the first and second electronic switches using the first and second control signals. The circuit includes a detection circuit configured to detect a current flowing through a control terminal of the first electronic switch during a transition portion, wherein the circuit is configured to adjust the first control signal and establish the second portion of the conduction sequence in response to the detected current.

In an example, a circuit for controlling at least two electronic switches in a parallel configuration between a power supply and a load. The circuit includes a control circuit to generate first and second control signals to control first and second electronic switches of the at least two electronic switches, and establish a conduction sequence of the first and second electronic switches using the first and second control signals. The circuit includes a detection circuit configured to detect a current flowing through a control terminal of the first electronic switch during a transition portion, wherein the circuit is configured to adjust the first control signal and establish the second portion of the conduction sequence in response to the detected current.

A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

An audio processing apparatus having an echo canceling mechanism is provided. An audio transmission circuit receives an input digital audio signal from an external device. A DAC circuit performs conversion according to the input digital audio signal to generate an output analog audio signal to an external display device for power amplification and playback. An ADC circuit performs analog-to-digital conversion on an amplified signal generated by a power amplification circuit and a received audio signal generated by an audio receiving device to generate an amplified digital signal and a received digital audio signal. A processor implements an echo canceling algorithm to perform echo cancellation according to the amplified digital signal and the received digital audio signal to generate an output digital audio signal to be transmitted to the external device through the audio transmission circuit.

An audio processing apparatus having an echo canceling mechanism is provided. An audio transmission circuit receives an input digital audio signal from an external device. A DAC circuit performs conversion according to the input digital audio signal to generate an output analog audio signal to an external display device for power amplification and playback. An ADC circuit performs analog-to-digital conversion on an amplified signal generated by a power amplification circuit and a received audio signal generated by an audio receiving device to generate an amplified digital signal and a received digital audio signal. A processor implements an echo canceling algorithm to perform echo cancellation according to the amplified digital signal and the received digital audio signal to generate an output digital audio signal to be transmitted to the external device through the audio transmission circuit.

In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.

In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.

The present disclosure relates to power management for digital-to-analog converters (DACs). As electronic devices and the components therein become increasingly smaller to satisfy the desire for more compact/portable devices, the operating voltage may be reduced to reduce the likelihood of shorts and/or voltage/current bleeds. To maintain comparable power output with the reduced operating voltage, the current may increase proportionally to the decrease in voltage. Consequently, in scaled devices and applications, high-current low-voltage regulators may be beneficial. As such, a low-dropout regulator (LDO) including one or more operational amplifiers and multiple pass devices may be implemented between a power supply and the DAC to regulate the power supply to the DAC. Moreover, the LDO may include one or more feedback loops to maintain a desired voltage regulation of the pass devices.

The present disclosure relates to power management for digital-to-analog converters (DACs). As electronic devices and the components therein become increasingly smaller to satisfy the desire for more compact/portable devices, the operating voltage may be reduced to reduce the likelihood of shorts and/or voltage/current bleeds. To maintain comparable power output with the reduced operating voltage, the current may increase proportionally to the decrease in voltage. Consequently, in scaled devices and applications, high-current low-voltage regulators may be beneficial. As such, a low-dropout regulator (LDO) including one or more operational amplifiers and multiple pass devices may be implemented between a power supply and the DAC to regulate the power supply to the DAC. Moreover, the LDO may include one or more feedback loops to maintain a desired voltage regulation of the pass devices.

A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.