A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

An interface circuit that interfaces a digital-to-analog converter (DAC) to a vertical-cavity surface emitting laser. The apparatus includes a first cascode amplifier that receives as input positive and negative differential outputs of the DAC and provides a positive amplified output and a negative amplified output, and a second cascode amplifier having a positive input and a negative input. The positive input of the second cascode amplifier being coupled to the positive amplified output of the first cascode amplifier. The second cascode amplifier is configured to generate a positive amplified current and a negative amplified current at a negative amplified output. The positive amplified current and the negative amplified current are combined and a resulting output current is provided as input to an anode of the laser. A transformer is coupled between the negative amplified output of the first cascode amplifier and the negative input of the second cascode amplifier.

An interface circuit that interfaces a digital-to-analog converter (DAC) to a vertical-cavity surface emitting laser. The apparatus includes a first cascode amplifier that receives as input positive and negative differential outputs of the DAC and provides a positive amplified output and a negative amplified output, and a second cascode amplifier having a positive input and a negative input. The positive input of the second cascode amplifier being coupled to the positive amplified output of the first cascode amplifier. The second cascode amplifier is configured to generate a positive amplified current and a negative amplified current at a negative amplified output. The positive amplified current and the negative amplified current are combined and a resulting output current is provided as input to an anode of the laser. A transformer is coupled between the negative amplified output of the first cascode amplifier and the negative input of the second cascode amplifier.

A device comprises a control circuit configured to control a plurality of quantum bits. The control circuit comprises a digital-to-analog converter circuit and switching circuitry coupled to an output of the digital-to-analog converter circuit. The switching circuitry is responsive to switch control signals to selectively connect the output of the digital-to-analog converter circuit to one or more of a plurality of signal paths to generate control signals to control the plurality of quantum bits.

A device comprises a control circuit configured to control a plurality of quantum bits. The control circuit comprises a digital-to-analog converter circuit and switching circuitry coupled to an output of the digital-to-analog converter circuit. The switching circuitry is responsive to switch control signals to selectively connect the output of the digital-to-analog converter circuit to one or more of a plurality of signal paths to generate control signals to control the plurality of quantum bits.

A wideband signal generator has one or more digital-to-analog converters (DAC), each of the one or more DACs having one or more pipes and a sample rate, a multiplexer to receive analog outputs from at least two pipes from the one or more DACs and multiplex the analog outputs and zero into an output stream, a bandpass filter to receive the output stream and filter out frequency components in the output stream that are outside a target frequency band and produce a radio frequency (RF) output signal in the in the target frequency band, and one or more processors configured to execute code that causes the one or more processors to generate digital samples and transfer the digital samples to the one or more DACs, the digital samples generated to produce analog outputs that cause the RF output signal to match the target RF frequency band.

A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.