Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.

A wideband signal generator has one or more digital-to-analog converters (DAC), each of the one or more DACs having one or more pipes and a sample rate, a multiplexer to receive analog outputs from at least two pipes from the one or more DACs and multiplex the analog outputs and zero into an output stream, a bandpass filter to receive the output stream and filter out frequency components in the output stream that are outside a target frequency band and produce a radio frequency (RF) output signal in the in the target frequency band, and one or more processors configured to execute code that causes the one or more processors to generate digital samples and transfer the digital samples to the one or more DACs, the digital samples generated to produce analog outputs that cause the RF output signal to match the target RF frequency band.

The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.

A device capable of detecting and capturing both cranking and operating events is provided. The device uses the same components to detect operating voltage for either electric or combustion vehicles, and to detect and facilitate capturing cranking events.

A device capable of detecting and capturing both cranking and operating events is provided. The device uses the same components to detect operating voltage for either electric or combustion vehicles, and to detect and facilitate capturing cranking events.

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a controllable resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the total resistance of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a controllable resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the total resistance of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

A method for providing an analog output signal includes (a) amplifying an analog first internal signal using a first Class-G amplifier to generate an analog first output signal, (b) providing the analog first output signal to a first load, and (c) configuring the first Class-G amplifier for an impedance of the first load by selecting one of a plurality of power supply rails to power the first Class-G amplifier at least partially based on a voltage across the first load. In some embodiments, an impedance of the first load may range from zero to 1,000 ohms.

A method for providing an analog output signal includes (a) amplifying an analog first internal signal using a first Class-G amplifier to generate an analog first output signal, (b) providing the analog first output signal to a first load, and (c) configuring the first Class-G amplifier for an impedance of the first load by selecting one of a plurality of power supply rails to power the first Class-G amplifier at least partially based on a voltage across the first load. In some embodiments, an impedance of the first load may range from zero to 1,000 ohms.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.