A method for testing a DAC comprising controlling the DAC digitally to cause it to produce a known desired analogue output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

A method for testing a DAC comprising controlling the DAC digitally to cause it to produce a known desired analogue output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.

A self-healing data converter system including a data converter; a parametric function module coupled to the data converter to receive a target performance requirement for a data converter and produce a set of function values to the data converter; an assistant module that captures data converter performance under one or more stress conditions; and a processing module coupled to the data converter to stress the data converter in accordance with one or more predetermined parameters and based on the target performance requirement and data converter performance, the processing module determines new parameters based on a self-healing method and applies the new parameters to produce a new set of function values for the data converter until a predetermined threshold is met to adaptively self-heal the data converter to changed conditions.

Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Methods and devices are provided in which a first parameter partial value (p1) is stored in a first memory (12) and a second parameter partial value (p2) is stored in a second memory (13). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p1) with the second parameter partial value (p2).

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

Methods and devices are provided in which a first parameter partial value (p1) is stored in a first memory (12) and a second parameter partial value (p2) is stored in a second memory (13). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p1) with the second parameter partial value (p2).