Mechanisms for generating dummy signals for use in reducing data dependent noise in DACs are disclosed. Disclosed mechanisms differentiate between odd and even bits of a digital data signal to be converted and generate dummy signals by inverting some of these bits and leaving other bits as they are (i.e. including them in their non-inverted form). One dummy signal is generated as a sequence of bits that is the same as a sequence of bits of a data signal except that every odd bit of the data signal is inverted. An alternative dummy signal is generated as a sequence of bits that is the same as a sequence of bits of a data signal except that every even bit is inverted. Generating dummy signals in this manner eliminates the need to use calibration, feedback, or transition detectors, advantageously resulting in increased timing margins and substantial power savings over existing implementations.

The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.

Disclosed are a method and system for generating clock signal of I.sup.2S audio bus, and a dac circuit. The method includes: reading an audio file transmitted by the I.sup.2S audio bus, by a master controller; the master controller reading sampling rate, data bit length, and number of channels of the audio file, and, calculating data volume for each frame according to the data bit length and the number of channels, generating a master clock signal according to a multiplier requirement of a slave controller on the master clock signal, a frequency of the master clock signal being f.sub.sX, wherein f.sub.s is the sampling rate, and X is a selected multiplier; and the slave controller receiving the master clock signal, and using the master clock signal as a clock source, to realize modulation and filtering for an audio digital-to-analog conversion.

Disclosed are a method and system for generating clock signal of I.sup.2S audio bus, and a dac circuit. The method includes: reading an audio file transmitted by the I.sup.2S audio bus, by a master controller; the master controller reading sampling rate, data bit length, and number of channels of the audio file, and, calculating data volume for each frame according to the data bit length and the number of channels, generating a master clock signal according to a multiplier requirement of a slave controller on the master clock signal, a frequency of the master clock signal being f.sub.sX, wherein f.sub.s is the sampling rate, and X is a selected multiplier; and the slave controller receiving the master clock signal, and using the master clock signal as a clock source, to realize modulation and filtering for an audio digital-to-analog conversion.

A DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter (low pass filter with peaking in the signal passband). The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency contents at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with at least one notch inductor Ln and at least one notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be configured with LC notch filters (with Ln notch inductors), and the peaking filter can be Ls peaking inductors coupled in series to the LC notch filters. The Ln notch inductors, Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ signal paths are implemented with differential DAC designs including passive reconstruction filters.

A DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter (low pass filter with peaking in the signal passband). The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency contents at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with at least one notch inductor Ln and at least one notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be configured with LC notch filters (with Ln notch inductors), and the peaking filter can be Ls peaking inductors coupled in series to the LC notch filters. The Ln notch inductors, Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ signal paths are implemented with differential DAC designs including passive reconstruction filters.

A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals.

A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

An electronic device may be configured to identify a load coupled to the device. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load to identify the load. The device may then take action based on the identification of the load. For example, a specific transducer may be identified as coupled to the electronic device and an appropriate equalization curve applied to an audio output of the device. The measurement of characteristics of the load may include controlling a reference generator according to a search algorithm, such as a step ramp or binary search, to identify the load. An analog-to-digital converter (ADC) may operate through the search algorithm to provide feedback to digital circuitry regarding how to proceed through the search algorithm to identify the load.