An electronic device may be configured to identify a load coupled to the device. The device may measure direct current (DC) and/or alternating current (AC) characteristics of the load to identify the load. The device may then take action based on the identification of the load. For example, a specific transducer may be identified as coupled to the electronic device and an appropriate equalization curve applied to an audio output of the device. The measurement of characteristics of the load may include controlling a reference generator according to a search algorithm, such as a step ramp or binary search, to identify the load. An analog-to-digital converter (ADC) may operate through the search algorithm to provide feedback to digital circuitry regarding how to proceed through the search algorithm to identify the load.

To reduce signal output and wiring to a D/A converter (DAC). A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.

To reduce signal output and wiring to a D/A converter (DAC). A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.

A digital to analog conversion circuit, DAC, comprises a number of serializing lanes, each serializing lane comprising at least two bit inputs, and each serializing lane being configured to output the two bit inputs serially via a serialized output port at a predetermined first clock rate. The DAC further comprises a number of non-serializing lanes, each non-serializing lane comprising at least two bit inputs and each non-serializing lane being configured to output the two bit inputs in parallel each via a separate parallel output port, at a second clock rate, which is half the clock rate of the first clock rate, and a current switching network comprising a bit input port for every one of the serialized output ports and for every one of the parallel output ports and being configured to produce a output current, based on the signals received via the bit input ports.

The present invention relates to a digital-analog conversion method and device for adjusting a reference current to be used in a digital-analog conversion, by using a common mode feedback device, and the digital-analog conversion method of the present invention comprises the steps of: generating a reference current by receiving a reference voltage; converting a digital signal into an analog signal by receiving the generated reference current; detecting a common mode voltage, which is the average value of a both-end voltage of the converted analog signal; comparing the detected common mode voltage with the reference voltage; generating a feedback signal on the basis of the comparison result; and adjusting the reference current according to the generated feedback signal.

Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.

A layout method for a current source array. A digital-to-analog converter (DAC) includes a plurality of complementary metal-oxide-semiconductor (CMOS) devices. Current sources for the CMOS devices are uniformly arranged in a one-dimensional array. The spacing between the current sources in the one-dimensional array is determined using a golden ratio.

A layout method for a current source array. A digital-to-analog converter (DAC) includes a plurality of complementary metal-oxide-semiconductor (CMOS) devices. Current sources for the CMOS devices are uniformly arranged in a one-dimensional array. The spacing between the current sources in the one-dimensional array is determined using a golden ratio.

Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits.

Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits.