Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits.

One example includes an R2R digital-to-analog converter (DAC) circuit. The circuit includes at least one scaling circuit configured to apply a scale-factor with respect to a nominal voltage range defined by a low-voltage rail and a reference voltage to define a scaled voltage range. The scale-factor can be positive and less than one. The circuit also includes an R2R ladder circuit configured to generate an analog ladder voltage corresponding to a digital input signal. The analog ladder voltage can have an amplitude in the scaled voltage range. The circuit further includes an output stage configured to apply an inverse of the scale-factor to the analog ladder voltage to generate an output voltage.

The present invention is a computationally-efficient compensator for removing nonlinear distortion. The compensator operates in a digital post-compensation configuration for linearization of devices or systems such as analog-to-digital converters and RF receiver electronics. The compensator also operates in a digital pre-compensation configuration for linearization of devices or systems such as digital-to-analog converters, RF power amplifiers, and RF transmitter electronics. The compensator effectively removes nonlinear distortion in these systems in a computationally efficient hardware or software implementation by using one or more factored multi-rate Volterra filters. Volterra filters are efficiently factored into parallel FIR filters and only the filters with energy above a prescribed threshold are actually implemented, which significantly reduces the complexity while still providing accurate results. For extremely wideband applications, the multi-rate Volterra filters are implemented in a demultiplexed polyphase configuration which performs the filtering in parallel at a significantly reduced data rate. The compensator is calibrated with an algorithm that iteratively subtracts an error signal to converge to an effective compensation signal. The algorithm is repeated for a multiplicity of calibration signals, and the results are used with harmonic probing to accurately estimate the Volterra filter kernels. The compensator improves linearization processing performance while significantly reducing the computational complexity compared to a traditional nonlinear compensator.

A method for testing a DAC is provided. The method includes controlling the DAC digitally to cause it to produce a known desired analog output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

A method for testing a DAC is provided. The method includes controlling the DAC digitally to cause it to produce a known desired analog output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

A semiconductor device with lower power consumption or a display device including the semiconductor device is provided. A circuit to which an N-bit signal is input includes a first digital-to-analog converter circuit to which an upper M-bit signal is input, a second digital-to-analog converter circuit to which a lower (NM)-bit signal is input, and an amplifier circuit. The amplifier circuit includes a first transistor and a second transistor. An output terminal of the first digital-to-analog converter circuit is electrically connected to a gate of the first transistor. An output terminal of the second digital-to-analog converter circuit is electrically connected to a substrate potential of the second transistor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. An output terminal of the amplifier circuit is electrically connected to a gate of the second transistor.

A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop.

A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop.

To prevent that the noise occurs at timing switching between PCM data and DSD data by a simple configuration.

An AV receiver 1 includes a mute circuit 5 that mutes output from a DAC 4, a detection circuit 6 that detects that a digital audio signal is zero data and supplies a detection signal, a microcomputer 2 that supplies a control signal at timing switching from PCM data to DSD data before switches from PCM mode that the DAC 4 converts PCM data into an analog audio signal to DSD mode that the DAC 4 converts DSD data into the analog audio signal, and an AND circuit 7 that activates the mute circuit 5 in case that the detection signal from the detection circuit 6 and the control signal from the microcomputer 2 are supplied.

A multi-channel audio system that can provide a variable sub-sample delay between two or more audio channels. In one embodiment, a variable timing clock generator generates multiple clock signals where each may have different phase, and the clock generator can vary the phase difference, in accordance with a sub-sample delay setting input. These clock signals are used by respective digital-to-analog converters (DACs) to convert the digital audio channels into analog form. In another embodiment, a variable delay block is added to an oversampling DAC, on a per channel basis. Other embodiments are also described and claimed.