A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop.

A noise-shaping signed digital-to-analog converter is described. A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code. The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop. The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop.

Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

A layout method for a current source array. A digital-to-analog converter (DAC) includes a plurality of complementary metal-oxide-semiconductor (CMOS) devices. Current sources for the CMOS devices are uniformly arranged in a one-dimensional array. The spacing between the current sources in the one-dimensional array is determined using a golden ratio.

A layout method for a current source array. A digital-to-analog converter (DAC) includes a plurality of complementary metal-oxide-semiconductor (CMOS) devices. Current sources for the CMOS devices are uniformly arranged in a one-dimensional array. The spacing between the current sources in the one-dimensional array is determined using a golden ratio.

One example includes an R2R digital-to-analog converter (DAC) circuit. The circuit includes at least one scaling circuit configured to apply a scale-factor with respect to a nominal voltage range defined by a low-voltage rail and a reference voltage to define a scaled voltage range. The scale-factor can be positive and less than one. The circuit also includes an R2R ladder circuit configured to generate an analog ladder voltage corresponding to a digital input signal. The analog ladder voltage can have an amplitude in the scaled voltage range. The circuit further includes an output stage configured to apply an inverse of the scale-factor to the analog ladder voltage to generate an output voltage.

A method for testing a DAC is provided. The method includes controlling the DAC digitally to cause it to produce a known desired analog output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

A method for testing a DAC is provided. The method includes controlling the DAC digitally to cause it to produce a known desired analog output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

To prevent that the noise occurs at timing switching between PCM data and DSD data by a simple configuration.

An AV receiver 1 includes a mute circuit 5 that mutes output from a DAC 4, a detection circuit 6 that detects that a digital audio signal is zero data and supplies a detection signal, a microcomputer 2 that supplies a control signal at timing switching from PCM data to DSD data before switches from PCM mode that the DAC 4 converts PCM data into an analog audio signal to DSD mode that the DAC 4 converts DSD data into the analog audio signal, and an AND circuit 7 that activates the mute circuit 5 in case that the detection signal from the detection circuit 6 and the control signal from the microcomputer 2 are supplied.

A multi-channel audio system that can provide a variable sub-sample delay between two or more audio channels. In one embodiment, a variable timing clock generator generates multiple clock signals where each may have different phase, and the clock generator can vary the phase difference, in accordance with a sub-sample delay setting input. These clock signals are used by respective digital-to-analog converters (DACs) to convert the digital audio channels into analog form. In another embodiment, a variable delay block is added to an oversampling DAC, on a per channel basis. Other embodiments are also described and claimed.