Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adjusts a clock associated with the transmitter. The duty-cycle distortion detector circuit facilitates digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on duty-cycle distortion error associated with output of the transmitter.

A method and circuit for performing vector-matrix multiplication may include converting an input vector of binary-encoded values into analog signals using one-bit DACs, and sequentially performing a vector-matrix multiplication operation for each bit-order. The method may also include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the multiplier to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector-matrix multiplication.

The present general inventive concept is directed to a method and system to generate a power signal, including summing a non-inverted reference signal and an inverted feedback signal to output a non-inverted first summation signal, summing an inverted reference signal and a non-inverted feedback signal to output an inverted second summation signal, receiving the first summation signal at a non-inverted input of a differential power output driver, and the second summation signal at an inverted input of the differential power output driver, outputting a non-inverted power signal to a first terminal of an impedance load from a non-inverted output of the differential power output driver, and outputting an inverted power signal to a second terminal of the load from an inverted output of the differential power output driver, the non-inverted power signal also being used as the non-inverted feedback signal, and the inverted power signal also being used as the inverted feedback signal.

The present disclosure relates to an electronic device. An analog-digital converter includes an input voltage provider configured to output the input voltage during a plurality of stages, a comparator configured to output a comparison result between the input voltage and one of a plurality of comparison reference voltages, a successive approximation register configured to output at least one bit among the plurality of bits of digital data based on the comparison result, and a digital-analog converter configured to provide the comparator with one comparison reference voltage among the plurality of the comparison reference voltages based on the at least one bit, wherein the digital-analog converter includes a plurality of transistors that are coupled in parallel with each other, the digital-analog converter configured to selectively receive a plurality of reference voltages to generate the one comparison reference voltage.

Disclosed is an output buffer circuit for a display driving apparatus, which generates an output voltage by using a bias current controlled by digital-to-analog conversion for interpolation data, the output buffer circuit including a decoder configured to output control data obtained by decoding interpolation data, and an output circuit configured to output an output voltage by using a bias current having the amount of current controlled by digital-to-analog conversion for the control data.

A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

The inventive concept relates to a method and system for cost-effectively predicting the dynamic nonlinearities of on-chip segmented digital-to-analog converter (DAC) and analog-to-digital-converter (ADC), by looping a DAC to an ADC, using a programmable-gain-amplifier (PGA) and an external load board. The method may include a first loopback step of supplying an output signal from a coarse DAC, to which a sinusoidal signal is supplied, to a coarse ADC and a fine ADC through an external load board, a second loopback step of supplying an output signal from a fine DAC, to which a sinusoidal signal is supplied, to the fine ADC and the coarse ADC through the load board, and a step of predicting dynamic nonlinearity of each of a DAC and an ADC by processing equations exhibiting dynamic nonlinearity of a sub-DAC and a sub-ADC, which are obtained in the first loopback step and the second loopback step.