The inventive concept relates to a method and system for cost-effectively predicting the dynamic nonlinearities of on-chip segmented digital-to-analog converter (DAC) and analog-to-digital-converter (ADC), by looping a DAC to an ADC, using a programmable-gain-amplifier (PGA) and an external load board. The method may include a first loopback step of supplying an output signal from a coarse DAC, to which a sinusoidal signal is supplied, to a coarse ADC and a fine ADC through an external load board, a second loopback step of supplying an output signal from a fine DAC, to which a sinusoidal signal is supplied, to the fine ADC and the coarse ADC through the load board, and a step of predicting dynamic nonlinearity of each of a DAC and an ADC by processing equations exhibiting dynamic nonlinearity of a sub-DAC and a sub-ADC, which are obtained in the first loopback step and the second loopback step.

A pulsed DC radar system is presented that includes a sliding window and DC offset. A method of pulsed DC radar operation, comprising an operation state, the operation state including initializing parameters for a current integration window; providing timing for the current integration window to an integrating filter based from a transmit pulse; providing a DC offset associated with the current integration window; and incrementing the current integration window to the next integration window to be timed from a next transmit pulse.

Embodiments of a gain control circuit and a wideband communication circuit that uses the gain control circuit are disclosed. In an embodiment, gain control circuit includes first and second output terminals to output gain control signals and first and second diode-connected transistors connected between a supply voltage and the first and second output terminals, which are connected to input terminals of a communication component circuit with a plurality of input transistors. The gain control circuit further includes a current digital-to-analog converter connected to the diode-connected transistors to generate first and second currents for the diode-connected transistors based on an N-bit input code, wherein a ratio of the first and second currents sets voltages of the gain control signals that are output from the gain control circuit to the communication component circuit to control signal gain provided by the communication component circuit.

Embodiments of a gain control circuit and a wideband communication circuit that uses the gain control circuit are disclosed. In an embodiment, gain control circuit includes first and second output terminals to output gain control signals and first and second diode-connected transistors connected between a supply voltage and the first and second output terminals, which are connected to input terminals of a communication component circuit with a plurality of input transistors. The gain control circuit further includes a current digital-to-analog converter connected to the diode-connected transistors to generate first and second currents for the diode-connected transistors based on an N-bit input code, wherein a ratio of the first and second currents sets voltages of the gain control signals that are output from the gain control circuit to the communication component circuit to control signal gain provided by the communication component circuit.

A non-volatile memory (NVM) crossbar for an artificial neural network (ANN) accelerator is provided. The NVM crossbar includes row signal lines configured to receive input analog voltage signals, multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each row signal line and MAC column signal line intersection, and a correction cell disposed at each row signal line and correction column signal line intersection. Each MAC cell includes one or more programmable NVM elements programmed to an ANN unipolar weight, and each correction cell includes one or more programmable NVM elements. Each MAC column signal line generates a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line generates a correction signal based on the input analog voltage signals and the correction cells. Each MAC signal is corrected based on the correction signal.

A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

A nicotine delivery device (200) for generating a mist containing nicotine for inhalation by a user. The device comprises a mist generator device (201) and a driver device (202). The driver device (202) is configured to drive the mist generator device (201) at an optimum frequency to maximise the efficiency of mist generation by the mist generator device (201).

A digital-to-analog conversion circuit, comprising: an R−2R resistive network (10) configured to be connected between an output end and a ground end; an output voltage selection unit (20) configured to be connected between the output end of the R−2R resistive network (10) and a voltage output terminal; an output voltage trimming unit (30), wherein the output voltage trimming unit (30) is provided between a 2R resistor on at least one branch of the R−2R resistive network (10) and the ground end.

A digital-to-analog conversion circuit, comprising: an R−2R resistive network (10) configured to be connected between an output end and a ground end; an output voltage selection unit (20) configured to be connected between the output end of the R−2R resistive network (10) and a voltage output terminal; an output voltage trimming unit (30), wherein the output voltage trimming unit (30) is provided between a 2R resistor on at least one branch of the R−2R resistive network (10) and the ground end.