A display compensation circuit includes a driver circuit including a digital-to-analog converter (DAC), the driver circuit configured to drive pixels of a display panel; and a compensation circuit including a current-mode sensing circuit and a reference current generator circuit, the compensation circuit configured to determine a value to compensate for pixel variations across the display panel, the reference current generator circuit configured to generate a reference current using the DAC of the driver circuit.

An audio driver circuit includes a modulator circuit configured to receive an audio input signal and produce a first modulated digital pulse signal. The first modulated digital pulse signal has a magnitude that switches between a supply power voltage and a supply ground voltage. The audio driver circuit also includes a switched driver circuit coupled to the modulator circuit to receive the first modulated digital pulse signal and configured to provide a second modulated digital pulse signal for driving an MOS (metal oxide semiconductor) output transistor. The second modulated digital pulse signal has a same timing pattern as the first modulated digital pulse signal and has a magnitude that tracks linearly with the magnitude of the audio input signal.

An audio driver circuit includes a modulator circuit configured to receive an audio input signal and produce a first modulated digital pulse signal. The first modulated digital pulse signal has a magnitude that switches between a supply power voltage and a supply ground voltage. The audio driver circuit also includes a switched driver circuit coupled to the modulator circuit to receive the first modulated digital pulse signal and configured to provide a second modulated digital pulse signal for driving an MOS (metal oxide semiconductor) output transistor. The second modulated digital pulse signal has a same timing pattern as the first modulated digital pulse signal and has a magnitude that tracks linearly with the magnitude of the audio input signal.

System and method for error amplification and processing. For example, the system includes: a signal processing unit configured to receive a reference signal and a feedback signal and generate a digital pulse signal, a frequency of the digital pulse signal being associated with a difference between the reference signal and the feedback signal; a counter configured to receive the digital pulse signal and generate a counter output signal based on at least information associated with the digital pulse signal; and a digital-to-analog converter configured to receive the counter output signal and generate an output signal based on at least information associated with the counter output signal.

Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive a downlink control message from a base station indicating a modulation and coding scheme (MCS) associated with an uplink transmission, a number of layers associated with the uplink transmission, or both. The UE may determine to adjust (for example, reduce) a first number of bits based on the MCS, the number of layers, or both. The first number of bits may include an effective number of bits (ENOB) supported at a digital-to-analog converter (DAC) of the UE, a number of bits (NOB) supported at a transmission front end (TxFE) component of the UE, or both. The UE may transmit the uplink transmission to the base station according to the adjusted first number of bits.

Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive a downlink control message from a base station indicating a modulation and coding scheme (MCS) associated with an uplink transmission, a number of layers associated with the uplink transmission, or both. The UE may determine to adjust (for example, reduce) a first number of bits based on the MCS, the number of layers, or both. The first number of bits may include an effective number of bits (ENOB) supported at a digital-to-analog converter (DAC) of the UE, a number of bits (NOB) supported at a transmission front end (TxFE) component of the UE, or both. The UE may transmit the uplink transmission to the base station according to the adjusted first number of bits.

Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

A video display unit includes a display panel with gate drivers and source drivers. Each of the source drivers receives an encoded analog signal representing a video stream over a transmission medium and decodes the signal to produce samples for output to the display. Gate driver control signals synchronize the gate drivers with the source drivers. The source drivers are integrated with the display panel glass in part or in whole. Amplifiers and level shifters of each source driver are implemented on the panel glass and the collector and decoder are not. Or, the amplifiers, shifters and collector are implemented on the panel glass and the decoder is not. Or, the amplifiers, shifters, collector and decoder of each source driver are implemented on the panel glass. The source drivers may drive a display of a mobile device. Thin-film transistors are used to implement the source drivers on glass.