A current transformer (CT) for the purpose of, for example, current measurement, that uses a power line as a first coil and a second coil for measurement purposes, is further equipped with a third coil. Circuitry connected to the third coil is adapted to inject a known reference signal to the third coil of the CT. The injected reference signal, i.e., current, generates signals in the first and second coils of the CT. The signal generated in the second coil is compared using circuitry attached thereto to the reference signal. Based on the results, and the difference between the expected results and the actual results, updated calibration parameters are determined. These provide improved accuracy when using the CT, for example for measurement of the like of current or phase of the primary coil when measurements are adjusted using the newly determined calibration parameters.

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

A method for light-to-digital conversion includes setting a time integrator circuit into a reference condition and starting to integrate charge from a sensor device for the duration of an integration time. An integration signal is generated and is indicative of the integrated charge. The integration signal is compared with an adjustable reference signal. A first count is generated when the comparison indicates that the integration signal has reached an integration range, wherein the integration range is defined by a low and a high voltage. A second count is generated when the comparison indicates that the integration signal has reached the adjustable reference signal. The adjustable reference signal is incremented in discrete steps when a second count has been generated. Then, the time integrator circuit is reset into the reference condition, when the comparison indicates that the integration signal has reached the integration range. The generated first counts is collected as first count signal and the generated second counts are collected as second count signal. Finally, a digital output signal is generated depending on the first count signal and the second count signal.

A digital-to-analog converter circuit including one or more digital-to-analog converter cells and a separate voltage protection circuit connected by a common output node. A first digital-to-analog converter cell includes a first transistor which is configured to be switched to a conductive state when the first digital-to-analog converter cell is activated. A first terminal of the first transistor is coupled to a defined potential, wherein a second terminal of the first transistor is coupled to a common output node of the one or more digital-to-analog converter cells. The digital-to-analog converter circuit further includes a voltage protection circuit coupled between the common output node of the one or more digital-to-analog converter cells and an output node of the digital-to-analog converter circuit to regulate a voltage between the common output node and the defined potential.

Embodiments provide a pre-distortion circuit and apparatus, a method and computer program for pre-distorting, a transmitter, a radio transceiver, a communication device, a mobile transceiver, a base station transceiver and a storage. The pre-distortion circuit (10) is configured for a digital quadrature signal. The pre-distortion circuit (10) comprises a first input (12) for an inphase component of the quadrature signal and a second input (14) for a quadrature component of the quadrature signal. The pre-distortion circuit 10 comprises a signal processing circuit (16) configured to determine whether polarities of the inphase component and quadrature component are equal, and to determine pre-distortion coefficients based on the amplitude of the inphase component, the amplitude of the quadrature component, and based on whether the polarities are equal.

Embodiments provide a pre-distortion circuit and apparatus, a method and computer program for pre-distorting, a transmitter, a radio transceiver, a communication device, a mobile transceiver, a base station transceiver and a storage. The pre-distortion circuit (10) is configured for a digital quadrature signal. The pre-distortion circuit (10) comprises a first input (12) for an inphase component of the quadrature signal and a second input (14) for a quadrature component of the quadrature signal. The pre-distortion circuit 10 comprises a signal processing circuit (16) configured to determine whether polarities of the inphase component and quadrature component are equal, and to determine pre-distortion coefficients based on the amplitude of the inphase component, the amplitude of the quadrature component, and based on whether the polarities are equal.

A list of digital elements to be sorted are converted to a group of analog signals. The group of analog signals are simultaneously compared to each other to determine the largest analog signal in the group. The largest analog signal is then compared to each of the analog signals in the group to determine which one or more of the analog signals in the group matches the largest analog signal. The matching one or more of the analog signals is removed from the group and the process is repeated until the group of analog signals have been sorted.

A list of digital elements to be sorted are converted to a group of analog signals. The group of analog signals are simultaneously compared to each other to determine the largest analog signal in the group. The largest analog signal is then compared to each of the analog signals in the group to determine which one or more of the analog signals in the group matches the largest analog signal. The matching one or more of the analog signals is removed from the group and the process is repeated until the group of analog signals have been sorted.

Included are: a first power source 3 configured to output a voltage required for a first gate bias voltage for turning a power amplifier 2 to an ON state; a second power source 4 configured to output a voltage required for a second gate bias voltage for turning the power amplifier 2 to an OFF state; a changeover switch 5 connected between the first power source 3 and the power amplifier 2 and configured to supply either the first gate bias voltage or the second gate bias voltage to the power amplifier 2 by switching a state between the first power source 3 and the power amplifier 2 to either an open state or a short-circuit state on the basis of a control signal related to on-off control of the power amplifier 2; and a resistance value varying unit 15 connected between the second power source 4 and the power amplifier 2 and configured such that a resistance value thereof is variable.