A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.

An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.

The fault diagnosis circuit includes a first line including a first resistor, having one end connected to the positive (+) terminal of a battery, and having the other end connected to a first input unit of an analog to digital converter (ADC); a second line including a second resistor, having one end connected to the positive (+) terminal of the battery, and having the other end connected to a first input unit of a comparator; and a third line including a third resistor, having one end connected to the negative (−) terminal of the battery, having a first other end connected to a second input unit of the ADC, and having a second other end connected to a second input unit of the comparator. A fault in a battery management system can be efficiently diagnosed using a smaller number of elements.

The fault diagnosis circuit includes a first line including a first resistor, having one end connected to the positive (+) terminal of a battery, and having the other end connected to a first input unit of an analog to digital converter (ADC); a second line including a second resistor, having one end connected to the positive (+) terminal of the battery, and having the other end connected to a first input unit of a comparator; and a third line including a third resistor, having one end connected to the negative (−) terminal of the battery, having a first other end connected to a second input unit of the ADC, and having a second other end connected to a second input unit of the comparator. A fault in a battery management system can be efficiently diagnosed using a smaller number of elements.

The present invention provides an amplifier including a DAC, an analog signal processing circuit, a digital signal processing circuit, a signal detector and a driving stage is disclosed. The DAC is configured to perform a digital-to-analog conversion operation on a digital input signal to generate an analog input signal. The analog signal processing circuit is configured to generate a first processed signal according to the analog input signal and a feedback signal. The digital signal processing circuit is configured to process the digital input signal to generate a second processed signal. The signal detector is configured to detect strength of the digital input signal to generate a mode selection signal. The driving stage is configured to refer to the mode selection signal to receive one of the first processed signal and the second processed signal to generate an output signal, wherein the feedback signal is generated by the output signal.

The present invention provides an amplifier including a DAC, an analog signal processing circuit, a digital signal processing circuit, a signal detector and a driving stage is disclosed. The DAC is configured to perform a digital-to-analog conversion operation on a digital input signal to generate an analog input signal. The analog signal processing circuit is configured to generate a first processed signal according to the analog input signal and a feedback signal. The digital signal processing circuit is configured to process the digital input signal to generate a second processed signal. The signal detector is configured to detect strength of the digital input signal to generate a mode selection signal. The driving stage is configured to refer to the mode selection signal to receive one of the first processed signal and the second processed signal to generate an output signal, wherein the feedback signal is generated by the output signal.

A signal source device includes at least one digital-to-analog converter, at least one connector, a first output path from the at least one digital-to-analog converter to the at least one connector, and a second output path from the at least one digital-to-analog converter to the at least one connector. A method of generating a analog signal includes generating at least one analog signal from at least one digital-to-analog converter, transmitting a first analog signal of the at least one analog signal along a first output path from the at least one digital-to-analog converter to at least one connector, and transmitting a second analog signal of the at least one analog signal along a second output path from the at least one digital-to-analog converter to the at least one connector.

A signal source device includes at least one digital-to-analog converter, at least one connector, a first output path from the at least one digital-to-analog converter to the at least one connector, and a second output path from the at least one digital-to-analog converter to the at least one connector. A method of generating a analog signal includes generating at least one analog signal from at least one digital-to-analog converter, transmitting a first analog signal of the at least one analog signal along a first output path from the at least one digital-to-analog converter to at least one connector, and transmitting a second analog signal of the at least one analog signal along a second output path from the at least one digital-to-analog converter to the at least one connector.