A circuit device includes a transfer gate, a charge compensation circuit, and a control circuit. The control circuit controls the charge compensation circuit. The charge compensation circuit discharges charge from an output node of the transfer gate when a voltage of an input signal to the transfer gate is in a first voltage range at a timing at which the transfer gate is turned off. The charge compensation circuit injects charge into the output node of the transfer gate when a voltage of the input signal to the transfer gate is in a second voltage range lower than that in the first voltage range at a timing at which the transfer gate is turned off.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

Embodiments of the disclosure provide a circuit structure and method to indicate a differential voltage polarity using a comparator. The circuit structure includes a digital-to-analog converter (DAC) coupled to a positive differential voltage, a negative differential voltage, and a reference voltage. The DAC generates an output based on the positive differential voltage, the negative differential voltage, and the reference voltage. A comparator has a first input coupled to one of the DAC output and the positive differential voltage, and a second input coupled to one of the reference voltage and the negative differential voltage. A multiplexer array is coupled to the comparator and transmits one of: the positive differential voltage and the negative differential voltage to the comparator, causing the comparator to output a differential voltage polarity; and the DAC output and the reference voltage, causing the comparator to output an approximated bit for the DAC output.

Techniques for generating digital outputs as stochastic bitstreams with activation function mapping are provided. In one aspect, a system includes: a shared circuitry component including a RNG for generating a sequence of random addresses to read a random sequence of digital voltage references stored in a LUT, and a DAC for converting the random sequence of digital voltage references into random analog voltage references V.sub.L; and a comparator(s) for comparing the random analog voltage references V.sub.L and input analog voltages V.sub.N in sequences of comparisons to produce sequences of digital pulses as stochastic bitstreams. A system having multiple comparators for simultaneously comparing each of the random analog voltage references V.sub.L against more than one of the input analog voltages V.sub.N in parallel is also provided, as is a method for generating digital outputs from input analog voltages V.sub.N.

Techniques for generating digital outputs as stochastic bitstreams with activation function mapping are provided. In one aspect, a system includes: a shared circuitry component including a RNG for generating a sequence of random addresses to read a random sequence of digital voltage references stored in a LUT, and a DAC for converting the random sequence of digital voltage references into random analog voltage references V.sub.L; and a comparator(s) for comparing the random analog voltage references V.sub.L and input analog voltages V.sub.N in sequences of comparisons to produce sequences of digital pulses as stochastic bitstreams. A system having multiple comparators for simultaneously comparing each of the random analog voltage references V.sub.L against more than one of the input analog voltages V.sub.N in parallel is also provided, as is a method for generating digital outputs from input analog voltages V.sub.N.

An audio player device includes a digital-to-analog converter (DAC), a startup circuit, a multiplexer and an output amplifier. The DAC converts audio data into a first signal and a second signal. The startup circuit gradually increases a level of a startup voltage according to a reference voltage during a predetermined period. The multiplexer outputs the startup voltage as a control voltage during the predetermined period, and switches to output the reference voltage as the control voltage after the predetermined period has elapsed. The output amplifier generates an audio signal according to the control voltage, the first signal and the second signal. The control voltage is used to set a common mode voltage of the output amplifier.

An audio player device includes a digital-to-analog converter (DAC), a startup circuit, a multiplexer and an output amplifier. The DAC converts audio data into a first signal and a second signal. The startup circuit gradually increases a level of a startup voltage according to a reference voltage during a predetermined period. The multiplexer outputs the startup voltage as a control voltage during the predetermined period, and switches to output the reference voltage as the control voltage after the predetermined period has elapsed. The output amplifier generates an audio signal according to the control voltage, the first signal and the second signal. The control voltage is used to set a common mode voltage of the output amplifier.

Quantum repeater systems and apparatus for quantum communication. In one aspect, a system includes a quantum signal receiver configured to receive a quantum field signal; a quantum signal converter configured to: sample quantum analog signals from a quantum field signal received by the quantum signal receiver; encode sampled quantum analog signals as corresponding digital quantum information in one or more qudits, comprising applying a hybrid analog-digital encoding operation to each quantum analog signal and a qudit in an initial state; decode digital quantum information stored in the one or more qudits as a recovered quantum field signal, comprising applying a hybrid digital-analog decoding operation to each qudit and a quantum analog register in an initial state; a quantum memory comprising qudits and configured to store digital quantum information encoded by the quantum signal converter; and a quantum signal transmitter configured to transmit the recovered quantum field signal.

Quantum repeater systems and apparatus for quantum communication. In one aspect, a system includes a quantum signal receiver configured to receive a quantum field signal; a quantum signal converter configured to: sample quantum analog signals from a quantum field signal received by the quantum signal receiver; encode sampled quantum analog signals as corresponding digital quantum information in one or more qudits, comprising applying a hybrid analog-digital encoding operation to each quantum analog signal and a qudit in an initial state; decode digital quantum information stored in the one or more qudits as a recovered quantum field signal, comprising applying a hybrid digital-analog decoding operation to each qudit and a quantum analog register in an initial state; a quantum memory comprising qudits and configured to store digital quantum information encoded by the quantum signal converter; and a quantum signal transmitter configured to transmit the recovered quantum field signal.

One example relates to a monitoring circuit that includes a capacitive digital-to-analog converter that receives a binary code, a reference voltage, a monitored voltage, and a ground reference, the capacitive digital-to-analog converter outputting an analog signal based on the binary code, the reference voltage, the monitored voltage, and the ground reference. The monitoring circuit further includes a comparator including a first input coupled to receive the analog signal and a second input coupled to the reference voltage, the comparator comparing the analog signal to the reference voltage and outputting a comparator signal based on the comparison. The monitoring circuit yet further includes a binary code generator that generates the binary code based on the comparator signal, the binary code approximating a magnitude of the monitored voltage.