A display compensation circuit includes a driver circuit including a digital-to-analog converter (DAC), the driver circuit configured to drive pixels of a display panel; and a compensation circuit including a current-mode sensing circuit and a reference current generator circuit, the compensation circuit configured to determine a value to compensate for pixel variations across the display panel, the reference current generator circuit configured to generate a reference current using the DAC of the driver circuit.

A spread spectrum clock generating system is provided. The digital frequency detecting unit is configured for receiving a reference signal and a feedback signal and for comparing the reference signal and the feedback signal to generate a frequency difference signal. The digital loop filtering unit is signally connected to the digital frequency detecting unit and outputs a clock controlling signal based on the frequency difference signal. The digital spread spectrum controlling unit is configured for receiving the reference signal to output a spread spectrum signal. The digital-analog converting unit is configured for converting the clock controlling signal to a first controlling signal and for converting the spread spectrum signal to a second controlling signal. The analog controlled oscillating unit is configured for receiving the first controlling signal and the second controlling signal to output a spread spectrum clock signal.

A spread spectrum clock generating system is provided. The digital frequency detecting unit is configured for receiving a reference signal and a feedback signal and for comparing the reference signal and the feedback signal to generate a frequency difference signal. The digital loop filtering unit is signally connected to the digital frequency detecting unit and outputs a clock controlling signal based on the frequency difference signal. The digital spread spectrum controlling unit is configured for receiving the reference signal to output a spread spectrum signal. The digital-analog converting unit is configured for converting the clock controlling signal to a first controlling signal and for converting the spread spectrum signal to a second controlling signal. The analog controlled oscillating unit is configured for receiving the first controlling signal and the second controlling signal to output a spread spectrum clock signal.

A device having a capacitive sampling structure that allows for removal of sampling noise can be implemented in a variety of applications. Noise cancellation can be achieved by storing on an auto-zero capacitor a scaled replica of kT/C noise by a mechanism of correlated sampling. In an example embodiment, a set of switches can be arranged such that, in switching, scaled thermal noise, generated in an acquisition phase in which a voltage signal is input to an input capacitor structure, is captured on an output capacitor structure and, in a conversion phase, the captured thermal noise is cancelled or compensated from an output of the output capacitor structure.

A device having a capacitive sampling structure that allows for removal of sampling noise can be implemented in a variety of applications. Noise cancellation can be achieved by storing on an auto-zero capacitor a scaled replica of kT/C noise by a mechanism of correlated sampling. In an example embodiment, a set of switches can be arranged such that, in switching, scaled thermal noise, generated in an acquisition phase in which a voltage signal is input to an input capacitor structure, is captured on an output capacitor structure and, in a conversion phase, the captured thermal noise is cancelled or compensated from an output of the output capacitor structure.

A controlled switch having N inputs and a single output (N2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.

Systems and methods to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a first current mode digital-to-analog converter (DAC) configured to multiply an input signal with a first current having a first amplitude to generate a first signal. The device can further include a second current mode DAC configured to multiply the input signal with a second current having a second amplitude to generate a second signal. The second amplitude can be less than the first amplitude. The device can further include a mixer configured to multiply the second signal with a clock signal to generate a third signal. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.

Systems and methods to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a first current mode digital-to-analog converter (DAC) configured to multiply an input signal with a first current having a first amplitude to generate a first signal. The device can further include a second current mode DAC configured to multiply the input signal with a second current having a second amplitude to generate a second signal. The second amplitude can be less than the first amplitude. The device can further include a mixer configured to multiply the second signal with a clock signal to generate a third signal. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.

Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.

An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC. A first DC level-shifting predriver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level-shifting predriver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream. An impedance matching module is coupled to an output of the protective device. The laser driver may be integrated on a CMOS communication chip.