An optical phased array comprising a row-column driving mechanism is disclosed that reduces the number of digital to analog converter (DAC) channels to the number of rows N and the total number of interface pin counts down to the number of columns plus the number of rows M+N. Disclosed herein are systems and architecture for thermal waveguide-based phase shifters which improve thermal efficiency by having multi-pass waveguides arranged proximate a heating element in a serpentine fashion, which enables an increase in phase shift without increasing the length or the power consumption of the heating element by increasing the total length of waveguide being heated by a singular heating element.

A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.

A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.

Disclosed herein are related to systems and methods for a power efficient successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a sample and digital to analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of multiple bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the multiple bits during a corresponding time period.

Disclosed herein are related to systems and methods for a power efficient successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a sample and digital to analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of multiple bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the multiple bits during a corresponding time period.

An apparatus for detecting a neural spike includes: a preprocessing circuit configured to remove a low-frequency component from a neural signal to form a low-frequency component removed neural signal, and amplify the low-frequency component removed neural signal; a comparing circuit configured to compare an output signal of the preprocessing circuit to a threshold signal; a merging circuit configured to merge spikes within a reference interval of an output signal of the comparing circuit into one peak, and to generate, based on the merging of the spikes, an output signal comprising pulses; and a counting circuit configured to count the pulses.

An apparatus for detecting a neural spike includes: a preprocessing circuit configured to remove a low-frequency component from a neural signal to form a low-frequency component removed neural signal, and amplify the low-frequency component removed neural signal; a comparing circuit configured to compare an output signal of the preprocessing circuit to a threshold signal; a merging circuit configured to merge spikes within a reference interval of an output signal of the comparing circuit into one peak, and to generate, based on the merging of the spikes, an output signal comprising pulses; and a counting circuit configured to count the pulses.

A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.

A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.

An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.