An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.

A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit (100) including a differential operational amplifier (130) having a first input node (E130a) and a second input node (E130b). A first current path (101) is coupled to a first reference input terminal (E100a) to apply a first reference potential (RefP) and the second current path (102) is coupled to a second reference input terminal (E100b) to apply a second reference potential (RefN). The at least one capacitor switch circuit (100) comprises a first controllable switch (111) being arranged between the second input node (E130a) of the differential operational amplifier (130) and the first current path (101). The at least one capacitor switch circuit (100) comprises a second controllable switch (112) being arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102).

A double-balanced radio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus includes a load network, a first set of resistive DAC driver circuits and a first mixing core. The first mixing core can receive first RF input signals from the first set of resistive DAC driver circuits and can provide a first mixed signal to the load network. The first mixing core includes a first input differential pair coupled to two first cross-coupled differential pairs. The first input differential pair can receive first RF input signals at respective first input nodes. Each of the two first cross-coupled differential pairs can receive first positive and negative local oscillator (LO) signals at corresponding first input nodes. The first mixing core can mix the first RF input signals with the first positive and negative LO signals.

A double-balanced radio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus includes a load network, a first set of resistive DAC driver circuits and a first mixing core. The first mixing core can receive first RF input signals from the first set of resistive DAC driver circuits and can provide a first mixed signal to the load network. The first mixing core includes a first input differential pair coupled to two first cross-coupled differential pairs. The first input differential pair can receive first RF input signals at respective first input nodes. Each of the two first cross-coupled differential pairs can receive first positive and negative local oscillator (LO) signals at corresponding first input nodes. The first mixing core can mix the first RF input signals with the first positive and negative LO signals.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a braided pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

A circuit includes a digital-to-analog conversion circuit, an amplifying circuit, a mixing circuit, and an analog-to-digital converter. The digital-to-analog conversion circuit is configured to receive and convert audio data in the digital domain and output audio data in the analog domain. The audio data includes a main-tone component. The amplifying circuit is configured to output an audio signal according to the audio data in the analog domain. The mixing circuit is configured to eliminate the main-tone component according to the audio data in the analog domain and the audio signal and to output a feedback signal. The analog-to-digital converter is configured to convert the feedback signal from the analog domain to the digital domain.

A circuit includes a digital-to-analog conversion circuit, an amplifying circuit, a mixing circuit, and an analog-to-digital converter. The digital-to-analog conversion circuit is configured to receive and convert audio data in the digital domain and output audio data in the analog domain. The audio data includes a main-tone component. The amplifying circuit is configured to output an audio signal according to the audio data in the analog domain. The mixing circuit is configured to eliminate the main-tone component according to the audio data in the analog domain and the audio signal and to output a feedback signal. The analog-to-digital converter is configured to convert the feedback signal from the analog domain to the digital domain.

A pop sound suppression method, an audio output circuit, and a terminal suppress a pop sound that is generated when an audio output circuit is in an alternating current (AC) coupling structure. The output circuit includes an output power amplifier, a common-mode voltage buffer, a reference voltage generation circuit, a powered-on pop sound suppression switch, and a common-mode switch. The powered-on pop sound suppression switch is configured to control, in a power-on process of the audio output circuit, a voltage level of an output node to be zero. The common-mode switch is configured to control, when a reference voltage level of the reference voltage generation circuit is zero, the voltage level of the output node to be equal to the reference level.

A pop sound suppression method, an audio output circuit, and a terminal suppress a pop sound that is generated when an audio output circuit is in an alternating current (AC) coupling structure. The output circuit includes an output power amplifier, a common-mode voltage buffer, a reference voltage generation circuit, a powered-on pop sound suppression switch, and a common-mode switch. The powered-on pop sound suppression switch is configured to control, in a power-on process of the audio output circuit, a voltage level of an output node to be zero. The common-mode switch is configured to control, when a reference voltage level of the reference voltage generation circuit is zero, the voltage level of the output node to be equal to the reference level.

Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.