Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

This disclosure provides an active envelope detector to generate an output voltage based on an input radio-frequency (RF) signal. The active envelope detector includes a plurality of transistors configured to operate in a sub-threshold mode and generate an output voltage based on the input RF signal. A delta-modulation analog-to-digital converter (ADC) and a sigma-delta modulation ADC are provided. Both ADCs include an implementation of the active envelope detector to receive input RF signals.

An A/D converter includes: an integrator circuit executing modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a modulation mode and a cyclic mode.

An A/D converter includes: an integrator circuit executing modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a modulation mode and a cyclic mode.

An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.

An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.

A method for improving performance of a superconducting, flux-quantizing analog to digital converter (SFADC), comprising the following steps. The first step involves providing a known digitally-modulated signal as an input to the SFADC. Another step provides for generating an output with the SFADC based on the known digitally-modulated signal. Another step provides for comparing the characteristics of the output with ideal characteristics to identify an individual rapid single flux quantum (RSFQ) element of the SFADC that is contributing one or more of noise and error to the output. Another step provides for altering one or more of a bias, a delay, and a temperature of the individual RSFQ element to reduce one or more of the noise and the error.

An A/D converter includes an integrator having an operational amplifier, a first feedback capacitor, and a second feedback capacitor, a quantizer outputting a quantization result of an output signal of the operational amplifier, and a D/A converter having a D/A converter capacitor. The D/A converter capacitor has a first terminal connected to an input terminal of the operational amplifier and a second terminal connected to an output terminal of the operational amplifier. The D/A converter performs a subtraction operation by repeating subtraction of charges accumulated in the first and second feedback capacitors based on the quantization result, and performs a cyclic operation by sequentially repeating subtraction and amplification of the charges accumulated in one of the first and second feedback capacitors based on the quantization result.

An A/D converter includes an integrator having an operational amplifier, a first feedback capacitor, and a second feedback capacitor, a quantizer outputting a quantization result of an output signal of the operational amplifier, and a D/A converter having a D/A converter capacitor. The D/A converter capacitor has a first terminal connected to an input terminal of the operational amplifier and a second terminal connected to an output terminal of the operational amplifier. The D/A converter performs a subtraction operation by repeating subtraction of charges accumulated in the first and second feedback capacitors based on the quantization result, and performs a cyclic operation by sequentially repeating subtraction and amplification of the charges accumulated in one of the first and second feedback capacitors based on the quantization result.

A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and summing the digital signal.