Video coding and decoding methods are described. An example method includes performing a conversion between a current video block of a video and a bitstream representation of the current video block by determining a first intra coding mode to be stored which is associated with the current video block using a differential coding mode, where the first intra coding mode associated with the current video block is determined according to a second prediction mode used by the differential coding mode, and where, in the differential coding mode, a difference between a quantized residual of an intra prediction of the current video block and a prediction of the quantized residual is represented in the bitstream representation for the current video block using a differential pulse coding modulation (DPCM) representation.

A method includes receiving a first cycle of an original cyclic signal. One or more cyclic parameters of the first cycle of the original cyclic signal are estimated. The original cyclic signal is predicted in counts, based at least partially upon the one or more cyclic parameters and one or more sensor parameters, to produce a predicted cyclic signal that corresponds to the original cyclic signal. The predicted cyclic signal includes biased, dual-state, differential pulse-code modulation (DPCM) data. A second cycle of the original cyclic signal is predicted based upon the predicted cyclic signal.

A method includes receiving a first cycle of an original cyclic signal. One or more cyclic parameters of the first cycle of the original cyclic signal are estimated. The original cyclic signal is predicted in counts, based at least partially upon the one or more cyclic parameters and one or more sensor parameters, to produce a predicted cyclic signal that corresponds to the original cyclic signal. The predicted cyclic signal includes biased, dual-state, differential pulse-code modulation (DPCM) data. A second cycle of the original cyclic signal is predicted based upon the predicted cyclic signal.

A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.

A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.

A vibration rectification error correction device includes a first filter that operates in synchronization with the measured signal, and a second filter that operates in synchronization with the reference signal, in which the first filter generates a third signal based on a first signal having a first group delay amount and a second signal having a second group delay amount, the second filter receives a signal based on the third signal and outputs a fourth signal, and a first vibration rectification error and a second vibration rectification error have different polarities.

A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

Devices and methods for digital to analog conversion (DAC) are provided, in which the analog outputs of an even number of digital to analog converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analog outputs are subtracted. Dither and filtering techniques may also be employed.