A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.

A Gas Chromatograph (GC) detector comprises a first circuit, a second circuit, a digital subtractor and a digital logic shared between one to many detector channels to provide a GC measurement in a digital form. The first circuit includes a first counter circuitry to provide a first counter output. The second circuit includes a second counter circuitry to provide a second counter output. The GC detector includes a digital subtractor to subtract the first counter output from the second counter output and provide a digital subtractor output. The GC detector further includes a digital logic shared between one to many detector channels to implement at least a portion of the first counter circuitry and the second counter circuitry. The digital logic to receive the digital subtractor output and provides the GC measurement in the digital form. The GC detector may be based on a Thermal Conductivity Detector (TCD) in which an integrator of a Sigma-Delta (-) A/D converter is eliminated and the/factor of the Sigma-Delta (-) A/D converter is accomplished in a digital form.

The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.

An method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

A signal processing unit for time of flight measurement includes an oscillation module, a transmission module, a detection module, a multiplier, an analog-to-digital-converter and a processing module. The oscillation module provides m reference phases. The transmission module generates a set of light impulses based on a selection phase selected out of the m reference phases. The detection module receives a set of reflections of the set of light impulses and to generate a detector signal based on the set of reflections. The multiplier obtains a result of a multiplication of the detector signal by a comparison phase. The analog-to-digital-converter converts the result of the multiplier into a digital signal. The processing module determines the comparison phase or the selection phase and calculates an approximate phase difference between the set of generated light impulses and the set of received reflections based on the digital signal.

An idle tone dispersion device outputs a frequency delta-sigma modulation signal obtained by using either one of a reference signal and a measured signal to perform frequency delta-sigma modulation of the other and dispersing an idle tone. The idle tone dispersion device includes n (n is any natural number equal to or larger than 2) frequency delta-sigma modulation sections and an adder configured to add up output signals of the n frequency delta-sigma modulation sections and output the frequency delta-sigma modulation signal. Each of the n frequency delta-sigma modulation sections uses either one of the reference signal and the measured signal to perform the frequency delta-sigma modulation of the other. At least one of the reference signal and the measured signal includes jitter including a frequency component higher than a frequency of an idle tone of an output signal of the frequency delta-sigma modulation section.

A method produces a digital signal from an analog signal. The method includes: producing a pulse-width-modulated actuation signal by a frequency converter, wherein the pulse-width-modulated actuation signal is produced over a number n of periods of the pulse width modulation such that the signal curve of the pulse-width-modulated actuation signal is identical in the respective periods; applying the actuation signal to a load; producing a bitstream with a predetermined bit repetition duration depending on an analog signal to be measured by a sigma-delta modulator, wherein the analog signal to be measured depends on the actuation signal and on the load, wherein a number m of bits are produced and stored with the predetermined bit repetition duration over a respective period of the pulse-width-modulated actuation signal; and summing corresponding bits of the respective periods in order to form the digital signal.

A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the i.sup.th time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.

An ultrasound probe (106) contains an array transducer (101) and a microbeamformer coupled to elements of the array. The microbeamformer comprises analog ASICs (102) with transmitters and amplifiers coupled to elements of the array (101). The microbeamformer also comprises analog to digital converters which convert received echo signals to digital data, and digital beamforming circuitry located in digital ASICs (103). The digital ASICs (103) are clocked at a lower core frequency than that of which the digital integrated circuit process of the digital ASICs (103) is capable, and the digital ASICs (103) are operated at a lower supply voltage than that for which the digital integrated circuit process is designed, both of which reduce power consumption by the microbeamformer.