Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

An method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

A signal processing unit for time of flight measurement includes an oscillation module, a transmission module, a detection module, a multiplier, an analog-to-digital-converter and a processing module. The oscillation module provides m reference phases. The transmission module generates a set of light impulses based on a selection phase selected out of the m reference phases. The detection module receives a set of reflections of the set of light impulses and to generate a detector signal based on the set of reflections. The multiplier obtains a result of a multiplication of the detector signal by a comparison phase. The analog-to-digital-converter converts the result of the multiplier into a digital signal. The processing module determines the comparison phase or the selection phase and calculates an approximate phase difference between the set of generated light impulses and the set of received reflections based on the digital signal.

Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

A phase locked loop comprises: a controllable oscillator 102; a variable divider arrangement 108, 110 which takes a signal from the controllable oscillator 102 and divides it by a variable amount to provide a lower frequency signal; a sigma-delta modulator 112 arranged to provide a control input to said variable divider arrangement 108, 110; and a phase detector triggered 104 by said lower frequency signal and a reference clock;
wherein said phase locked loop is arranged to be operable in a normal mode in which the controllable oscillator 102 is controlled by a voltage from said phase detector 104 and a calibration mode in which the controllable oscillator 102 is controlled digitally by a signal from a calibration module 114 which receives an input from said variable divider arrangement 108, 110.

A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.

Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.

Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

The present disclosure relates to a compressive encoding apparatus, a compressive encoding method, a decoding apparatus, a decoding method, and a program which can provide a lossless compression technology having a higher compression rate. An encoding unit of the compressive encoding apparatus converts M bits of a -modulated digital signal into N bits (M>N) with reference to a first conversion table, and when the M bits are not able to be converted into the N bits with the first conversion table, converts the M bits into the N bits with reference to a second conversion table. When the number of bit patterns of the N bits is P, the first conversion table is a table storing (P1) number of codes having higher generation frequencies for past bit patterns, and the second conversion table is a table storing (P1) number of codes having higher generation frequencies for past bit patterns, which follow those of the first conversion table. The present disclosure is applicable to a compressive encoding apparatus that compressively encoding an audio signal, and the like, for example.

A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.