A device for supplying an ultrasonic transducer including a power interface configured to provide an analog power signal, called supply signal, to the ultrasonic transducer, and further including a delta-sigma modulator configured to produce a delta-sigma modulator of a sinusoidal signal, called drive signal, and provide a digital signal, called control signal, to control said power interface. Also an ultrasonic device powered by such a supply device, an ultrasonic head including such ultrasonic devices and an ultrasonic system including such an ultrasonic head.

A Gas Chromatograph (GC) detector comprises a first circuit, a second circuit, a digital subtractor and a digital logic shared between one to many detector channels to provide a GC measurement in a digital form. The first circuit includes a first counter circuitry to provide a first counter output. The second circuit includes a second counter circuitry to provide a second counter output. The GC detector includes a digital subtractor to subtract the first counter output from the second counter output and provide a digital subtractor output. The GC detector further includes a digital logic shared between one to many detector channels to implement at least a portion of the first counter circuitry and the second counter circuitry. The digital logic to receive the digital subtractor output and provides the GC measurement in the digital form. The GC detector may be based on a Thermal Conductivity Detector (TCD) in which an integrator of a Sigma-Delta (Σ-Δ) A/D converter is eliminated and the Σ factor of the Sigma-Delta (Σ-Δ) A/D converter is accomplished in a digital form.

In a transmission system of an audio signal etc., circuit enlargement is suppressed and deterioration of transmitting signal is reduced. A transmission system including a transmitting apparatus including a first delta-sigma modulator outputting first multi-bit delta-sigma modulated signals of three or more bits and a first code modulator code-modulating first signals of two or more bits located in bit positions higher than a predetermined bit position of the first multi-bit delta-sigma modulated signals based on at least part of a second signal located in one or more bit positions not higher than the predetermined bit position and outputting a plurality of modulated signals; a transmission path transmitting the second signal and the plurality of modulated signals; and a receiving apparatus including a first demodulator demodulating the plurality of the received modulated signals based on at least part of the received second signal is provided.

An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (V.sub.in) and a plurality of converter circuits (105.sub.1-105.sub.N). Each converter circuit (105.sub.j) comprises a comparator circuit (70.sub.j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70.sub.j). Furthermore, each converter circuit (105.sub.j) comprises a one-bit current-output DAC (110.sub.j) having an input directly controlled from the output of the comparator circuit (70.sub.j) and an output connected to the second input of the comparator circuit (70.sub.j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits

A linear voltage regulator includes a converter circuit that provides a serial bitstream having a pulse density that is indicative of a difference between a regulated voltage of the linear voltage regulator and a reference voltage. The linear voltage regulator also includes a digital to analog converter circuit that includes an input to receive the serial bitstream. The digital to analog converter circuit includes an averager circuit that produces an output signal to control a voltage of a control terminal of a power transistor of the linear voltage regulator for regulating the regulated voltage based on the pulse density of the serial bitstream.

The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).

A transmitter apparatus that performs beamforming with phase correction uses power detectors present between power amplifiers (PAs) and antennas are used to measure power amplitudes on at least two transmission paths. The sum and difference of these amplitudes are then evaluated to determine a phase difference therebetween. A phase of one signal contributing to the sum and difference may be modified until the sum and difference are the same. Based on an amount of phase modification, a correction signal may be sent to a beamforming circuit to provide phase correction during beamforming.

A photoelectric conversion apparatus includes a light receiving circuit configured to convert light into an electrical signal, a readout circuit configured to read out an analog signal corresponding to the electrical signal, a ΔΣ A/D converter configured to convert the analog signal into a digital signal, and a control circuit configured to change a gain of the photoelectric conversion apparatus in accordance with a change of a driving mode of the photoelectric conversion apparatus. The analog signal read out by the readout circuit is an analog current signal. The readout circuit includes a variable resistor on a signal path for supplying the analog current signal to the ΔΣ A/D converter. The control circuit changes the gain of the photoelectric conversion apparatus by changing a resistance value of the variable resistor.

The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.