A system for generating an RFPWM signal comprises a delta sigma modulator having a plurality of outputs, a phase-locked loop comprising a plurality of phase quantization outputs, at least one multiplexer having a plurality of signal inputs, a plurality of selector inputs, and at least one output, the signal inputs communicatively connected to the phase quantization outputs of the phase-locked loop and the selector inputs electrically connected to the outputs of the delta sigma modulator, and a driver having an input communicatively connected to the output of the multiplexer and an output generating an RFPWM signal. A method of generating an RFPWM signal is also described.

A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

A processing system with a microarchitectural feature for mitigation of differential power analysis and electromagnetic analysis attacks can include a memory, a processor, and a mitigation response unit. The processor can include an instruction predictor that comprises a storage device for storing metadata associated with corresponding instruction blocks. The mitigation response unit is coupled to the instruction predictor to write and read the metadata associated with the corresponding instruction blocks. The mitigation response unit is configured to determine a mitigation technique for an instruction block based on an electromagnetic or power signature corresponding to execution of the instruction block and metadata associated with the instruction block.

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

A ring oscillator-based analog-to-digital converter (ADC). The ring oscillator-based ADC includes a ring oscillator and a transition detector. The ring oscillator may include a set of inverters coupled in a ring wherein an output of an inverter is coupled to an input of a successive inverter in the ring. The transition detector is configured to detect transitions of outputs of the inverters by comparing outputs of two separate inverters at two consecutive time instances. The transition detector may include two sets of registers configured to store outputs of the set of inverters at two consecutive time instances, respectively, and a set of comparators configured to compare the outputs stored in the two sets of registers. Each comparator may be configured to compare an output of one inverter at a first time instance and an output of another inverter at a second time instance.

A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.

A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.