Collating text strings having Unicode encoding includes receiving two text strings S=s.sub.1s.sub.2 . . . s.sub.n and T=t.sub.1t.sub.2 . . . t.sub.m. When the two text strings are not identical, there is a smallest positive integer p for which the two text strings differ. The process looks up the characters s.sub.p and t.sub.p in a predefined lookup table. If either of these characters is missing from the lookup table, the collation of the text strings is determined using the standard Unicode comparison of the text strings s.sub.ps.sub.p+1 . . . s.sub.n and t.sub.pt.sub.p+1 . . . t.sub.m. Otherwise, the lookup table assigns weights v.sub.p and w.sub.p for the characters s.sub.p and t.sub.p. When v.sub.pw.sub.p, these weights define the collation order of the strings S and T. When v.sub.p=w.sub.p, the collation of S and T is determined recursively using the suffix strings s.sub.p+1 . . . s.sub.n and t.sub.p+1 . . . t.sub.m.

Collating text strings having Unicode encoding includes receiving two text strings S=s.sub.1s.sub.2 . . . s.sub.n and T=t.sub.1t.sub.2 . . . t.sub.m. When the two text strings are not identical, there is a smallest positive integer p for which the two text strings differ. The process looks up the characters s.sub.p and t.sub.p in a predefined lookup table. If either of these characters is missing from the lookup table, the collation of the text strings is determined using the standard Unicode comparison of the text strings s.sub.ps.sub.p+1 . . . s.sub.n and t.sub.pt.sub.p+1 . . . t.sub.m. Otherwise, the lookup table assigns weights v.sub.p and w.sub.p for the characters s.sub.p and t.sub.p. When v.sub.pw.sub.p, these weights define the collation order of the strings S and T. When v.sub.p=w.sub.p, the collation of S and T is determined recursively using the suffix strings s.sub.p+1 . . . s.sub.n and t.sub.p+1 . . . t.sub.m.

One example includes a VID signal decoder circuit. The circuit includes a coarse resolution decoder that receives a VID signal. The VID signal can be encoded with a digital value of an output voltage. The coarse resolution decoder can decode the VID signal to generate a first digital signal. The circuit also includes a fine resolution decoder that receives the VID signal and to decode the VID signal to generate a second digital signal. The circuit further includes a multiplexer to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal. The first and second states of the selection signal can be based on a relative amplitude of the first and second digital signals.

One example includes a VID signal decoder circuit. The circuit includes a coarse resolution decoder that receives a VID signal. The VID signal can be encoded with a digital value of an output voltage. The coarse resolution decoder can decode the VID signal to generate a first digital signal. The circuit also includes a fine resolution decoder that receives the VID signal and to decode the VID signal to generate a second digital signal. The circuit further includes a multiplexer to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal. The first and second states of the selection signal can be based on a relative amplitude of the first and second digital signals.

An arithmetic encoder for encoding a plurality of symbols having symbol values is configured to derive an interval size information for an arithmetic encoding of one or more symbol values to be encoded based on a plurality of state variable values representing statistics of a plurality of previously encoded symbol values with different adaptation time constants. The arithmetic encoder is configured to map a first state variable value, or a scaled and/or rounded version thereof, using a lookup-table and to map a second state variable value, or a scaled and/or rounded version thereof using the lookup-table, in order to obtain the interval size information describing an interval size for the arithmetic encoding of one or more symbols to be encoded. Further arithmetic encoders, arithmetic decoders, video encoders, video decoder, methods for encoding, methods for decoding and computer programs are also disclosed which are based on the same concept and on other concepts.

An arithmetic encoder for encoding a plurality of symbols having symbol values is configured to derive an interval size information for an arithmetic encoding of one or more symbol values to be encoded based on a plurality of state variable values representing statistics of a plurality of previously encoded symbol values with different adaptation time constants. The arithmetic encoder is configured to map a first state variable value, or a scaled and/or rounded version thereof, using a lookup-table and to map a second state variable value, or a scaled and/or rounded version thereof using the lookup-table, in order to obtain the interval size information describing an interval size for the arithmetic encoding of one or more symbols to be encoded. Further arithmetic encoders, arithmetic decoders, video encoders, video decoder, methods for encoding, methods for decoding and computer programs are also disclosed which are based on the same concept and on other concepts.

A system and method to compress application control data, such as weights for a layer of a convolutional neural network, is disclosed. A multi-core system for executing at least one layer of the convolutional neural network includes a storage device storing a compressed weight matrix of a set of weights of the at least one layer of the convolutional network and a decompression matrix. The compressed weight matrix is formed by matrix factorization and quantization of a floating point value of each weight to a floating point format. A decompression module is operable to obtain an approximation of the weight values by decompressing the compressed weight matrix through the decompression matrix. A plurality of cores executes the at least one layer of the convolutional neural network with the approximation of weight values to produce an inference output.

A system and method to compress application control data, such as weights for a layer of a convolutional neural network, is disclosed. A multi-core system for executing at least one layer of the convolutional neural network includes a storage device storing a compressed weight matrix of a set of weights of the at least one layer of the convolutional network and a decompression matrix. The compressed weight matrix is formed by matrix factorization and quantization of a floating point value of each weight to a floating point format. A decompression module is operable to obtain an approximation of the weight values by decompressing the compressed weight matrix through the decompression matrix. A plurality of cores executes the at least one layer of the convolutional neural network with the approximation of weight values to produce an inference output.

Techniques and apparatus for parallel decompression are described. In one embodiment, for example, an apparatus to provide parallel decompression may include at least one memory and logic for a decompression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine decompression information of a compressed data unit, annotate the compressed data unit with at least a portion of the decompression information to generate an annotated data unit, parallel-decode the annotated data unit to generate a plurality of intermediate elements, and decode and merge the plurality of intermediate elements to generate a decompressed data unit. Other embodiments are described and claimed.

This application discloses a decoding method, a decoding device, and a readable storage medium. The decoding method can perform a simple logic operation on the corresponding specified bits in the first bitstream, and generate the corresponding fourth bitstream accordingly to obtain information before encoding. The logic design of this decoding method is simple, which can reduce the complexity of logic circuit design and improve the reliability of decoding.