Systems, apparatuses, and methods related to host-based bit string conversion are described. A conversion component may be deployed on a host computing system and configured to perform operations on bit strings to selectively convert the bit string between various numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The conversion component may comprise a processing device that may be coupled to one or more memory resources. The memory resource of the conversion component may be configured to receive a bit string having a first format. The processing device of the conversion component coupled to the memory resource may be configured to format or convert the bit string to a second format.

Circuits, methods, and apparatus for efficiently implementing encoding and decoding between binary and multilevel data.

In example implementations, an apparatus is provided. The apparatus comprises a processor and a non-transitory computer readable storage medium encoded with instructions executable by a processor, the non-transitory computer-readable storage medium. The non-transitory computer readable storage medium includes instructions to receive a plurality of data having N bits, wherein each of the N bits is binary, select a set of code words for each one of the plurality of data, wherein the code words have M bits, wherein each of the M bits is binary having an approximately equal number of ones and zeros, wherein a value of M is greater than N, and print a reflection and inversion invariant code based on the set of code words to represent data of the plurality of data.

A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8×8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 8×8 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8×8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.

A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.

Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

A method compares text strings having Unicode encoding. The method receives a first string S=s.sub.1s.sub.2 . . . s.sub.n and a second string T=t.sub.1t.sub.2 . . . t.sub.m, where s.sub.1, s.sub.2, . . . , s.sub.n and t.sub.1, t.sub.2, . . . , t.sub.m are Unicode characters. The method computes a first string weight for the first string S according to a weight function . When S consists of ASCII characters, (S)=S. when S includes one or more non-replaceable non-ASCII characters, the first string weight (S) is a concatenation of an ASCII weight prefix .sub.A(S) and a Unicode weight suffix .sub.U(S). The method also computes a second string weight for the second text string T. Equality of the strings is tested using the string weights.

A method compares text strings having Unicode encoding. The method receives a first string S=s.sub.1s.sub.2 . . . s.sub.n and a second string T=t.sub.1t.sub.2 . . . t.sub.m, where s.sub.1, s.sub.2, . . . , s.sub.n and t.sub.1, t.sub.2, . . . , t.sub.m are Unicode characters. The method computes a first string weight for the first string S according to a weight function . When S consists of ASCII characters, (S)=S. when S includes one or more non-replaceable non-ASCII characters, the first string weight (S) is a concatenation of an ASCII weight prefix .sub.A(S) and a Unicode weight suffix .sub.U(S). The method also computes a second string weight for the second text string T. Equality of the strings is tested using the string weights.

Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.