Patent classifications
H03M7/14
Probabilistic shaping techniques for high performance coherent optical transceivers
A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.
Bit string conversion invoking bit strings having a particular data pattern
Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.
Bit string conversion invoking bit strings having a particular data pattern
Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.
Efficient data encoding
Circuits, methods, and apparatus for efficiently implementing encoding and decoding between binary and multilevel data.
Hybrid comparison for unicode text strings consisting primarily of ASCII characters
A method compares text strings having Unicode encoding. The method receives a first string S=s.sub.1s.sub.2 . . . s.sub.n and a second string T=t.sub.1t.sub.2 . . . t.sub.m, where s.sub.1, s.sub.2, . . . , s.sub.n and t.sub.1, t.sub.2, . . . , t.sub.m are Unicode characters. The method computes a first string weight for the first string S according to a weight function . When S consists of ASCII characters, (S)=S. When S consists of ASCII characters and some accented ASCII characters that are replaceable by ASCII characters, (S)=g(s.sub.1)g(s.sub.2) . . . g(s.sub.n), where g(s.sub.i)=s.sub.i when s.sub.i is an ASCII character and g(s.sub.i)=s.sub.i when s.sub.i is an accented ASCII character that is replaceable by the corresponding ASCII character s.sub.i. The method also computes a second string weight for the second text string T. Equality of the strings is tested using the string weights.
Hybrid comparison for unicode text strings consisting primarily of ASCII characters
A method compares text strings having Unicode encoding. The method receives a first string S=s.sub.1s.sub.2 . . . s.sub.n and a second string T=t.sub.1t.sub.2 . . . t.sub.m, where s.sub.1, s.sub.2, . . . , s.sub.n and t.sub.1, t.sub.2, . . . , t.sub.m are Unicode characters. The method computes a first string weight for the first string S according to a weight function . When S consists of ASCII characters, (S)=S. When S consists of ASCII characters and some accented ASCII characters that are replaceable by ASCII characters, (S)=g(s.sub.1)g(s.sub.2) . . . g(s.sub.n), where g(s.sub.i)=s.sub.i when s.sub.i is an ASCII character and g(s.sub.i)=s.sub.i when s.sub.i is an accented ASCII character that is replaceable by the corresponding ASCII character s.sub.i. The method also computes a second string weight for the second text string T. Equality of the strings is tested using the string weights.
Methods and devices for encoding and decoding binary data
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for encoding binary data are provided. One of the methods includes: obtaining a multimedia file from a storage device, extracting multiple bytes of binary data from the multimedia file, converting the binary data into 7-bit encoded data using an encoding algorithm, and sending one or more signals comprising the 7-bit encoded data to a remote computing device. The converting includes identifying multiple bits of data, each corresponding to a predetermined bit position of one of the bytes of binary data, generating one or more bytes of combined-bit data by combining the identified bits of data, generating one or more bytes of remaining-bit data, and generating the 7-bit encoded data by concatenating the one or more bytes of combined-bit data and the one or more bytes of remaining-bit data.
BIT STRING CONVERSION
Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision.
BIT STRING CONVERSION
Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision.
IMPAIRMENT COMPENSATION TECHNIQUES FOR HIGH PERFORMANCE COHERENT OPTICAL TRANSCEIVERS
A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8x8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 88 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8x8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.