Embodiments herein provide a method for predicting iterations for decoding an encoded data at an electronic device. The method includes: receiving, by the electronic device, the encoded data; detecting, by the electronic device, signal parameters associated with the encoded data; predicting, by the electronic device, one of a cyclic redundancy check (CRC) failure, CRC success, and a CRC uncertainty in iterations for decoding the encoded data based on the signal parameters using a Neural Network (NN) model.

A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

A method and device for energy-efficient decoders. The decoder device can include a plurality of decoder modules configured to process an input data signal having a plurality of forward error correction (FEC) codewords. This plurality of decoder modules can include at least a first decoder followed by a second decoder. The first decoder can be low-power to first eliminate most of the errors of the codewords and the second decoder can be high-performance to correct the remaining errors. Alternatively, the first decoder can be high-performance to correct the codewords until the low-power decoder can correct the remaining errors. A classifier module can be included to determine portions of the codewords to be directed to any one of the plurality of decoder modules. These implementations can be extended to use additional decoders with different decoding algorithms and optimized to maximize decoder performance given a maximum power constraint.

Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

A device includes an interconnect and a plurality of devices connected to the interconnect. The plurality of devices includes a first interface connected to the interconnect and a second interface connected to the interconnect. The plurality of devices further includes a first memory bank connected to the interconnect and a second memory bank connected to the interconnect. The plurality of devices further includes an external memory interface connected to the interconnect and a controller configured to establish virtual channels among the plurality of devices connected to the interconnect.

Methods and systems for analyzing data are disclosed. An example method can comprise receiving a first data signal, decoding the first data signal, determining a second data signal based on the decoded first data signal, and determining a modulation error ratio based on a difference between the first data signal and the second data signal.

A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

A method for constructing parity-check concatenated polar codes and an apparatus therefor are disclosed. According to an embodiment of the inventive concept, a method for constructing a polar code includes receiving a code length, a message length, and channel information, generating an information set and a parity set of polar codes based on the received code length, the received message length, and the received channel information, and generating a parity node including the information set of elements based on the generated information set and the generated parity set.