A data error correction method, apparatus, device, and readable storage medium are disclosed. The method includes: acquiring target data to be error-corrected; performing error correction on the target data using an error-correcting code to obtain first data; judging whether the performing of the error correction on the target data is successful; responsive to the performing of the error correction on the target data being not successful, correcting the target data using a target neural network to obtain second data, determining the second data as the target data, and continuing to perform the error correction on the target data again; and responsive to the performing of the error correction on the target data being successful, determining the first data as the error-corrected target data.

A system for generating a parity check matrix for low-density parity-check (LDPC) codes includes a memory and a processing circuitry that retrieves a base matrix from the memory. The base matrix represents sets of valid and invalid positions for a set of circulant matrices. The processing circuitry determines a value for each valid position based on a heuristic function. The value for each valid position indicates a corresponding circulant matrix of the set of circulant matrices. The processing circuitry replaces each valid position with the corresponding circulant matrix based on the determined value, and each invalid position with a null matrix, to generate the parity check matrix. The parity check matrix thus generated has a high girth and equal distribution of cycles within the parity check matrix.

A system is provided to receive, by a controller, a first request to read a first page of data stored in a storage device which comprises a plurality of non-volatile memory units. The system accumulates, by a calculation module, a syndrome associated with the first page of data to obtain a syndrome weight. In response to determining that the syndrome weight is less than a predetermined threshold, the system writes, by the controller, the first page of data to a destination page of the storage device. In response to determining that the syndrome weight is greater than the predetermined threshold and that a current number of retries is less than a predetermined number: the system executes a retry process between the calculation module and a data flip engine of the controller to update the syndrome weight; and the system increments the current number of retries.

A system is provided to receive, by a controller, a first request to read a first page of data stored in a storage device which comprises a plurality of non-volatile memory units. The system accumulates, by a calculation module, a syndrome associated with the first page of data to obtain a syndrome weight. In response to determining that the syndrome weight is less than a predetermined threshold, the system writes, by the controller, the first page of data to a destination page of the storage device. In response to determining that the syndrome weight is greater than the predetermined threshold and that a current number of retries is less than a predetermined number: the system executes a retry process between the calculation module and a data flip engine of the controller to update the syndrome weight; and the system increments the current number of retries.

A method, system, and ASIC chip for comparing a bit error rate (BER) to a forward error correction (FEC) threshold to determine a Q margin for a codeblock; wherein the BER corresponds to the number of errors in a given amount of data; where a codeblock of a FEC corresponds to the given amount of data; wherein the FEC threshold corresponds to the maximum amount of errors per codeblock that the FEC is able to remove per given amount of data; wherein the Q margin corresponds to a difference between the BER and the FEC threshold.

A method, system, and ASIC chip for comparing a bit error rate (BER) to a forward error correction (FEC) threshold to determine a Q margin for a codeblock; wherein the BER corresponds to the number of errors in a given amount of data; where a codeblock of a FEC corresponds to the given amount of data; wherein the FEC threshold corresponds to the maximum amount of errors per codeblock that the FEC is able to remove per given amount of data; wherein the Q margin corresponds to a difference between the BER and the FEC threshold.

Methods and apparatuses for generating optimized LDPC codes are proposed. One of the methods is a method for generating an optimized LDPC code for an asymmetric transmission channel. The method includes receiving an initial LDPC code for the asymmetric transmission channel. Further, the method includes performing a density evolution threshold optimization for the initial LDPC code in order to obtain the optimized LDPC code for the asymmetric transmission channel. A uniformly mixed symmetric channel density for the asymmetric transmission channel is used in the density evolution threshold optimization.

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

A forward error correction (FEC) data generator has an input for at least two datastreams for which FEC data shall be generated in a joint manner, each datastream having a plurality of symbols. A FEC data symbol is based on a FEC source block possibly having a subset of symbols of the at least two data streams. The FEC data generator further has a signaling information generator configured to generate signaling information for the FEC data symbol regarding which symbols within the at least two datastreams belong to the corresponding source block by determining pointers to start symbols within a first and a second datastream, respectively, of the at least two datastreams and a number of symbols within the first datastream and second datastreams, respectively, that belong to the corresponding source block.

Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that performs FEC encoding, in a first clock domain, on the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data.