Interleaved ECC coding for key-value data storage devices. In one embodiment, a controller includes a memory interface including a namespace database; an ECC engine; a controller memory; and an electronic processor. The electronic processor is configured to receive a host write command, determine whether write access was setup as a key-value (KV) namespace in the namespace database and is associated with the host write command, and control the ECC engine and the memory interface to perform one or more program operations on the data in the memory using the interleaved ECC coding and based on the host write command in response to determining that the write access was setup as the KV namespace in the namespace database and the KV namespace is associated with the host write command.

In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.

In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.

In one embodiment, a method includes transmitting pulse power on two wire pairs, the pulse power comprising a plurality of high voltage pulses with the high voltage pulses on the wire pairs offset between the wire pairs to provide continuous power, performing low voltage fault detection on each of the wire pairs between the high voltage pulses, and transmitting data on at least one of the wire pairs during transmittal of the high voltage pulses. Data transmittal is suspended during the low voltage fault detection.

Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

An LDPC parity check matrix includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word.