Patent classifications
H03M13/03
METHOD OF CONSTRUCTING FLAT XOR CODES FROM INTEGER INDEXED TANNER GRAPHS
A method for defining an erasure code for system having a predetermined number of data disks is disclosed. The method includes selecting step, constructing step, determining step and repeating step. The selecting step includes selecting a predetermined acceptable number of failures for the system. The constructing step includes constructing a first Tanner graph for two failures acceptable system having predetermined number of data disks. The determining step includes determining erasure code from the first Tanner graph. The repeating step includes repeating the constructing step and the determining step by increasing the acceptable number of failures by one and constructing another Tanner graph in response to the increased acceptable number of failures by increasing number of parity nodes until the predetermined number of failures for the system is reached.
Device and method for generating a multi-kernel polar code
A device for generating a multi-kernel polar code x.sub.N of length N and dimension K on the basis of a first transformation matrix G.sub.N of size N×N that defines a first multi-kernel polar code includes a processor configured to generate a second transformation matrix G′.sub.N of size N×N by permuting the order of at least two columns of a sub-matrix of the first transformation matrix G.sub.N, and generate the multi-kernel polar code x.sub.N an the basis of x.sub.N=u.sub.N.Math.G′.sub.N, wherein u.sub.N=(u.sub.0, . . . , u.sub.N−1) is a vector of size N, with the elements u.sub.i, i=0, . . . N−1, corresponding to an information bit if i∈I, I being a set of K information bit indices, and u.sub.i=0, if i∈F, F being a set of N−K frozen bit indices.
Network coding using an outer coding process
Systems, methods, and devices for encoding and decoding data packets for transmission across a data network. To encode, data packets are first subjected to a an outer code process to result in outer coded packets. The outer coded packets are then divided into generations or groups of outer coded packets, each group or generation having an equal number of packets. Output packets are then created by forming random linear combinations of the outer coded packets from a specific generation or group of outer coded packets. The coefficients for the various elements of each linear combination is selected from a Galois field of values. To decode the incoming packets, enough packets are received until an iterative decoding process can be initiated.
Signal processing device, magnetic information playback device, and signal processing method
The invention provides a signal processing device, including: an extraction section that extracts, from an input digital signal, a decoding target signal at an extraction timing that has been determined as a timing for extracting the decoding target signal; a decoding section that decodes the decoding target signal by estimating, by a maximum likelihood decoding, a candidate for a decoding result of the decoding target signal extracted by the extraction section and detecting a maximum likelihood decoding result; and an adjustment section that adjusts the extraction timing using a likelihood of the candidate for the decoding result estimated by the decoding section.
CRC code calculation circuit and method thereof, and semiconductor device
A CRC code calculation circuit including: an extraction circuit that extracts a calculation target packet that is a target of CRC calculation from a signal frame inputted as a parallel signal of a first bit length; a shift circuit that generates, when a bit length of the calculation target packet does not match an integral multiple of the first bit length, data A of a bit length that is the integral multiple of the first bit length by shifting the calculation target packet such that a last bit of the calculation target packet is positioned at a least significant bit, and adding “0” to a most significant bit side of a head bit of the shifted calculation target packet; and a calculation circuit that generates a CRC code by performing a CRC calculation on the data A based on an initial value “0” stored in a register.
Data encoding method and apparatus, data decoding method and apparatus, OLT, ONU, and PON system
A data encoding method and apparatus and a data decoding method and apparatus in a passive optical network (PON) system include collecting N data blocks at a physical coding sublayer and generating valid data by combining the N data blocks, generating a payload, where the payload includes the valid data, performing FEC encoding on the payload to generate a check part, and generating a codeword structure. The synchronization header may be located at the head or the tail of the codeword structure.
Data encoding method and apparatus, data decoding method and apparatus, OLT, ONU, and PON system
A data encoding method and apparatus and a data decoding method and apparatus in a passive optical network (PON) system include collecting N data blocks at a physical coding sublayer and generating valid data by combining the N data blocks, generating a payload, where the payload includes the valid data, performing FEC encoding on the payload to generate a check part, and generating a codeword structure. The synchronization header may be located at the head or the tail of the codeword structure.
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.
Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
Method and apparatus for joint rate matching and deinterleaving
Digital communications systems employ Forward Error Correction (FEC) for robustness against fading, noise and interference. FEC is designed to support different code rates to meet different requirements. Different code rates may be achieved by performing puncturing or repetition operation. At the receiver the decoding may be performed on the baseline code rate to enable common decoder module. To enable this capability, the input to the decoder of the error correcting code must be initialized to zeros for the bit positions corresponding to bits that are not transmitted. For high throughput systems, it is not efficient to initialize particular bit positions to zero. A method and apparatus are disclosed for joint Rate Matching and deinterleaving that enable the decoder to begin the decoding operation on the received bits without explicitly initializing the punctured bit positions to zero.