A transmitting apparatus includes: a low density parity check (LDPC) encoder configured to encode information bits to generate parity bits based on a parity check matrix according to a code rate of 8/15 and a code length of 64800; an interleaver configured to interleave an LDPC codeword including the information bits and parity bits; and a mapper configured to map the interleaved LDPC codeword onto constellation points, wherein the parity check matrix comprises an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is defined by a specific table indicating indices of rows at which a value “1” is positioned in a 0-th column of an i-th column group in the parity check matrix.

The present invention discloses a decoding path selection device for decoding codewords generated by convolutional codes or turbo codes encoders in error correction codes, the decoding path selection device comprising: a branch metrics calculation unit for receiving incoming signals and calculating branch metrics values; a programmable generalized trellis router for generating a decoding path control signal according to the turbo code or convolutional code specification employed by one of communications standards; a multiplexer for receiving the branch metrics values from the branch metrics calculation unit and the decoding path control signal from the programmable generalized trellis router and selecting a corresponding branch metrics value; a recursive calculation unit, connected after the multiplexer and for receiving the corresponding branch metrics value from the multiplexer; and an a-posteriori probability calculation unit, connected after the recursive calculation unit and for calculating a final decoding result.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A signal compensation method and device, where the method includes receiving a signal sequence suffering from intersymbol interference (ISI), setting a first filtering coefficient to perform filter compensation on the received signal sequence to obtain a first compensation signal sequence, setting a balance filtering coefficient to perform filter compensation on the first compensation signal sequence to obtain a balance compensation result, where the balance filtering coefficient is obtained by adjusting, according to a first compensation error, a balance filtering coefficient set last time, performing sequence estimation on the balance compensation result and outputting the balance compensation result, where the first compensation error adjusts the balance filtering coefficient set to perform filter compensation on the first compensation signal sequence in an iterative manner, thereby effectively compensating for the signal sequence suffering from the ISI, and improving performance of an optical fiber communications system.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.

A memory controller including: a fault determination circuit to receive first parity, second parity, and data read out from a first row of a memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit to store a repair parity for repairing a fault of a row of a plurality of rows of the memory device, wherein the plurality of rows constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; and a recovery circuit to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row.

A coding and modulation apparatus and method are presented. The apparatus (10) comprises an encoder (11) that encodes input data into cell words, and a modulator (12) that modulates said cell words into constellation values of a non-uniform constellation. The modulator (12) is configured to use, based on the total number M of constellation points of the constellation and the signal-to-noise ratio SNR in dB, a non-uniform constellation from a group of constellations comprising one or more of predetermined constellations defined by the constellation position vector w.sub.0 . . . b−1, wherein b=M/4.