Patent classifications
H03M13/25
Transmitting apparatus and interleaving method thereof
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
Transmitting apparatus, receiving apparatus, and signal processing method thereof
A transmitting apparatus, a receiving apparatus and methods of controlling these apparatuses are provided. The transmitting apparatus includes: a baseband packet generator configured to, based on an input stream including a first type stream and a second type stream, generate a baseband packet including a header and payload data corresponding to the first type stream; a frame generator configured to generate a frame including the baseband packet; a signal processor configured to perform signal-processing on the generated frame; and a transmitter configured to transmit the signal-processed frame, wherein the header includes a type of the payload data in the baseband packet and the number of the first type stream packets in the baseband packet.
Transmission device, transmission method, reception device, and reception method
An FEC coder in a transmission device according to an exemplary embodiment of the present disclosure performs BCH coding and LDPC coding based on whether a code length of the LDPC coding is a 16k mode or a 64k mode. A mapper performs mapping in an I-Q coordinate to perform conversion into an FEC block, and outputs pieces of mapping data (cells). The mapper defines different non-uniform mapping patterns with respect to different code lengths even an identical coding rate is used by the FEC coder. This configuration improves a shaping gain for different error correction code lengths in a transmission technology in which modulation of the non-uniform mapping pattern is used.
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.
Transmitter and parity permutation method thereof
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order.
Multiple component codes based generalized low-density parity-check codes for high-speed optical transport
Systems and methods for data transport, including encoding streams of input data using generalized low-density parity check (GLDPC) encoders, the one or more GLDPC encoders being configured to generate GLDPC coded data streams using a plurality of component local codes to improve error correction strength, employ single-parity checks and two or more local block codes during generation of the GLDPC codes, and enable continuous tuning of code rate using the generated GLDPC codes. Signals may be generated using mappers, the mappers configured to assign bits of signals to signal constellations and to associate the bits of the signals with signal constellation points. The signal may be modulated using an I/Q or 4-D modulator composed of one polarization beam splitter, two I/Q modulators, and one polarization beam combiner. The modulated signals are multiplexed using a mode-multiplexer, transmitted over a transmission medium, and the signals are received and decoded using GLDPC decoders.
SOFT DECODER PARAMETER OPTIMIZATION FOR PRODUCT CODES
In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.
METHOD OF LDPC CODE ENCODING FOR REDUCING SIGNAL OVERHEAD AND APPARATUS THEREFOR
A method of low-density parity check (LDPC) code encoding and an apparatus therefor are disclosed. The LDPC code encoding method includes determining whether code block cyclic redundancy check (CRC) is attached to a code block based on a channel state or a required error rate. Signal overhead is reduced via selective application of the code block CRC.
FEC Decoding Apparatus and Method
A decoding apparatus and method. When all the code words in the to-be-decoded group meet that a checksum is 0, forward error correction (FEC) decoding is not performed, and only the sign bit decision is performed. That is, in a process of performing multiple times of decoding on each code word, FEC decoding is not always performed every time. This reduces power consumption required by FEC decoding.
System and method for processing control information
A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.