Apparatuses, systems, and techniques to decode encoded data for fifth-generation (5G) new radio (NR). In at least one embodiment, a processor includes one or more circuits to select one or more data decoding operations to decode one or more 5G signals based, at least in part, on a sparsity of data received by the processor.

A coding and modulation apparatus and method are presented. The apparatus comprises an encoder that encodes input data into cell words, and a modulator that modulates said cell words into constellation values of a non-uniform constellation. The modulator is configured to use, based on the total number M of constellation points of the constellation, the signal-to-noise ratio SNR and the number n of the dimension of the constellation, an n-dimensional non-uniform constellation from a group of constellations, wherein each constellation point of an n-dimensional constellation diagram is defined by an n-tupel of constellation values, said n-tupel of constellation values defining parameter settings of a transmission parameter used by a transmission apparatus for transmitting a transmission stream obtained by conversion of said constellation values.

A coding and modulation apparatus and method are presented. The apparatus comprises an encoder that encodes input data into cell words, and a modulator that modulates said cell words into constellation values of a non-uniform constellation. The modulator is configured to use, based on the total number M of constellation points of the constellation, the signal-to-noise ratio SNR and the number n of the dimension of the constellation, an n-dimensional non-uniform constellation from a group of constellations, wherein each constellation point of an n-dimensional constellation diagram is defined by an n-tupel of constellation values, said n-tupel of constellation values defining parameter settings of a transmission parameter used by a transmission apparatus for transmitting a transmission stream obtained by conversion of said constellation values.

Examples relate to a Low-Density Parity-Check Code (LDPC) decoder apparatus or device, to an LDPC decoder system and to corresponding methods and computer programs. The LDPC decoder apparatus comprises input circuitry and processing circuitry. The processing circuitry is configured to obtain a syndrome of a codeword via the input circuitry. The processing circuitry is configured to perform LDPC iterative decoding using the obtained syndrome, wherein the changes to be applied to the codeword due to the LDPC iterative decoding are recorded by applying the changes to a surrogate codeword. The processing circuitry is configured to record changes to be applied to the codeword due to the LDPC iterative decoding by storing the surrogate codeword in a memory structure.

An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence.

A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.

The present disclosure relates to data processing methods and apparatus. One example method includes obtaining a first data block, where the first data block is a data block obtained by dividing first optical path data, adding clock simplified padding data and the first data block into a target information bit in a first data frame to form target data, where the target information bit is an information bit that is preset in the first data frame and that is used to pad optical path data, encoding the target data by using a first error correction encoding scheme to obtain a first code block that has a mapping relationship with the first data frame, where the first error correction encoding scheme matches a frame structure of the first data frame, and sending the first code block.

Devices and methods for enhancing forward error correction techniques for communications using chirp spread spectrum are disclosed. Systems, devices, and methods for error correction coding and decoding are described. On the coding side, K bits of data are sequentially loaded into an M bit by N bit (M×N) matrix in a first direction as Q sequences of D bits, each D bit row of data in the M×N matrix is coded with an error correction code to generate an M bit row of coded data, each Q bit column in the M×N matrix is coded with the error correction code to generate N bits of coded data, N sequences of M bits are sequentially unloaded from the M×N matrix in a second direction, and a chirp signal is generated having a plurality of chirps.

The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.