An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

The invention relates to method and apparatus for improving the performance of communication systems using Run length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

The invention relates to method and apparatus for improving the performance of communication systems using Run length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.

A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.

A method of encoding input data includes receiving the input data that includes a plurality of input words including a first input word and a second input word, generating a plurality of converted words including a first converted word and a second converted word, the first converted word being based at least on the first input word, the second converted word being based on the first converted word and the second input word, identifying a key value based on the plurality of converted words, and generating a plurality of coded words based on the key value and the plurality of converted words.

A method of encoding input data includes receiving the input data that includes a plurality of input words including a first input word and a second input word, generating a plurality of converted words including a first converted word and a second converted word, the first converted word being based at least on the first input word, the second converted word being based on the first converted word and the second input word, identifying a key value based on the plurality of converted words, and generating a plurality of coded words based on the key value and the plurality of converted words.

Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.