A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.

Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.

Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.

Decoders are provided for memory systems. A decoder includes a seed generator that generates seeds based on a physical address corresponding to a read request from a host; a descrambling module that receives a sequence from a storage area among, multiple storage areas, corresponding to the physical address, and descrambles the sequence using the seeds to generate multiple descrambled sequences; and a selector that selects one of descrambled sequences based on syndrome weight values of the descrambled sequences.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter device may segment a plurality of bits of a communication into a first set of bits and a second set of bits; process the first set of bits using a first processing chain and the second set of bits using a second processing chain, wherein the first set of bits is mapped to most significant bits (MSBs) of one or more symbols of a composite constellation and the second set of bits is mapped to least significant bits (LSBs) of the one or more symbols of the composite constellation, and wherein the composite constellation is formed from a plurality of lower order constellations; modulate the first set of bits and the second set of bits to generate a set of modulated symbols; and transmit the set of modulated symbols. Numerous other aspects are provided.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter device may segment a plurality of bits of a communication into a first set of bits and a second set of bits; process the first set of bits using a first processing chain and the second set of bits using a second processing chain, wherein the first set of bits is mapped to most significant bits (MSBs) of one or more symbols of a composite constellation and the second set of bits is mapped to least significant bits (LSBs) of the one or more symbols of the composite constellation, and wherein the composite constellation is formed from a plurality of lower order constellations; modulate the first set of bits and the second set of bits to generate a set of modulated symbols; and transmit the set of modulated symbols. Numerous other aspects are provided.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.