A message-passing iterative decoding method of an associated LFSR sequence (or M-sequence) as a simplex code, to a parity matrix H. The method includes determining a set of parity polynomials with a low weight obtained by combining the parity equations of the matrix H. For each combination of K such polynomials of this set, an extended parity matrix H.sub.ext is built by concatenating elementary parity matrices associated with the parity polynomials of said combination. The combination of parity polynomials leading to a bipartite graph not having cycles with a length 4 and having a minimum number of cycles with lengths 6 and 8 is selected. Then, the LFSR sequence is decoded using the bipartite graph corresponding to the selected combination. This decoding method enables the false-alarm rate to be substantially reduced.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

A method includes encoding a data object in accordance with dispersed storage error encoding parameters to produce sets of encoded data slices having sets of slice names. The dispersed storage error encoding parameters includes a pillar width number of encoded data slices. The data object is associated with a unique source name and each slice name includes a reference to the unique source name. The method further includes executing a distributed agreement protocol using the unique source name and coefficients regarding a plurality of storage units of the dispersed storage network (DSN) to produce a ranking of the plurality of storage units. The method further includes identifying the pillar width number of storage units of the plurality of storage units based on the ranking of the storage units. The method further includes sending the plurality of sets of encoded data slices to the pillar width number of storage units for storage therein.

A method includes encoding a data object in accordance with dispersed storage error encoding parameters to produce sets of encoded data slices having sets of slice names. The dispersed storage error encoding parameters includes a pillar width number of encoded data slices. The data object is associated with a unique source name and each slice name includes a reference to the unique source name. The method further includes executing a distributed agreement protocol using the unique source name and coefficients regarding a plurality of storage units of the dispersed storage network (DSN) to produce a ranking of the plurality of storage units. The method further includes identifying the pillar width number of storage units of the plurality of storage units based on the ranking of the storage units. The method further includes sending the plurality of sets of encoded data slices to the pillar width number of storage units for storage therein.

A method and computing device for use in a dispersed storage network (DSN) to recover corrupt encoded data slices. In response to a request to storage units of the DSN for encoded data slices corresponding to a data segment, the computing device of a receives at least a decode threshold number of encoded data slices and at least one integrity error message that provides an indication of a corrupt encoded data slice, such that less than a decoded threshold number of valid slices is received. Utilizing at least one correction approach involving stored integrity data, the computing device then corrects the corrupt slice(s) to produce a decode threshold number of encoded data slices in order to decode the corresponding data segment. A variety of correction approaches may be employed, including a multi-stage approach that utilizes data from both valid and invalid slices.

A method and computing device for use in a dispersed storage network (DSN) to recover corrupt encoded data slices. In response to a request to storage units of the DSN for encoded data slices corresponding to a data segment, the computing device of a receives at least a decode threshold number of encoded data slices and at least one integrity error message that provides an indication of a corrupt encoded data slice, such that less than a decoded threshold number of valid slices is received. Utilizing at least one correction approach involving stored integrity data, the computing device then corrects the corrupt slice(s) to produce a decode threshold number of encoded data slices in order to decode the corresponding data segment. A variety of correction approaches may be employed, including a multi-stage approach that utilizes data from both valid and invalid slices.

The present embodiments provide a method and an apparatus for determining a frame boundary of an FEC frame, and a decoding system. The method includes receiving data, where the data includes N+P consecutive symbols, N consecutive symbols constitute a first data block, and N consecutive symbols constitute a second data block; obtaining s parameter values corresponding to the first data block. The method also includes determining a first iterative item and a second iterative item and determining, according to the s parameter values corresponding to the first data block, s parameter values corresponding to the second data block. Additionally, the method includes determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame.

A storage device includes a recording medium, a first memory storing first data read from the recording medium, and a controller. The controller searches for read target data in the first data by executing a parity check on second data that is in the first data and starts at a first position, while executing the parity check, determining whether or not an interruption condition is satisfied, storing the second data in a second memory when the parity check completes without the interruption condition being satisfied and a result of a completed parity check satisfies a first condition, and executing a parity check on third data that is in the first data and starts at a second position, responsive to the interruption condition being satisfied and responsive to the result of the completed parity check not satisfying the first condition.

In an error detector 4, a symbol mask generation unit 27 generates a mask pattern, an error detection unit 30 detects and counts an error in a portion corresponding to Flit in a PAM4 signal from a device under test W, and a Flit error detection unit 31 detects and counts an FEC symbol error in a portion corresponding to Flit for each ECC group, and determines in which the number of FEC symbol errors exceeds a threshold value to be a Flit error.