Techniques described and suggested herein include systems and methods for optimizing performance characteristics by differentiating data storage device types for data archives stored on data storage systems using redundancy coding techniques. For example, redundancy coded shards, which may include identity shards that contain unencoded original data of archives, may be stored on different types of data storage devices to optimize for various retrieval use cases and implemented environments. Implementing systems may monitor various performance characteristics so as to adaptively account for changes to some or all of the monitored parameters.

A method for sending forward error correction (FEC) configuration information by a sending apparatus in a multimedia system is provided. The method includes sending source FEC configuration information for an FEC source packet to a receiving apparatus, wherein the source FEC configuration information includes information related to an FEC source or repair packet that is sent first among at least one FEC source or repair packet if an FEC source or repair packet block includes the at least one FEC source or repair packet.

Systems and methods presented herein provide for an LTE wireless communication system operating in a Radio Frequency (RF) band with a conflicting wireless system. The LTE system includes an eNodeB operable to detect a plurality of UEs in the RF band, to generate LTE frames for downlink communications to the UEs, and to time-divide each LTE frame into a plurality of subframes. The eNodeB is also operable to condense the downlink communications into a first number of the subframes that frees data from a remaining number of the subframes in each LTE frame, and to burst-transmit the first number of the subframes of each LTE frame in the RF band.

Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

The present invention relates to data transmission/reception methods using a polar coding scheme, and devices for supporting same. The method for transmitting data by using polar coding in a wireless access system, according to one embodiment of the present invention, may comprise the steps of deriving Bhattacharyya parameters according to data bits input for finding noise-free channels among equivalent channels; allocating data payloads comprising data bits and cyclic redundancy check (CRC) bits to the found noise-free channels; inputting the data payloads into a polar encoder; and transmitting code bits output by the polar encoder, wherein the CRC bits may be allocated to better noise-free channels, among the noise-free channels indicated by the Bhattacharyya parameters, than the data bits.

Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.

Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.

A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

According to one embodiment, a semiconductor memory device includes an encoder configured to generate an error correction code with respect to data, a processor configured to perform interleaving with respect to the data output from the encoder after the generation of the error correction code by the encoder, and a memory configured to store a process result from the processor.